Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, from self-driving cars to learning machines. Join us to transform the future through technological innovation.
\nYou are a skilled ASIC Digital Design Engineer with over 5 years of design verification experience. You thrive in collaborative settings, communicate clearly, and have a strong technical foundation in simulation tools and scripting. Driven by curiosity and a passion for technology, you’re eager to make an impact on Data Center, AI/ML, and 5G solutions.
\nDeveloping and validating high-speed interface IP in digital/mixed-signal environments. Planning tests, coverage, and assertions for robust verification. Building verification environments from specifications. Applying advanced techniques: constrained random, coverage, assertions, formal verification. Debugging simulations and performing RTL, GLS, and co-simulations. Supporting customers and improving development processes.
\nAdvance Synopsys’ IP quality and reliability. Accelerate development for Data Center, AI/ML, and 5G. Drive innovation through modern verification methods. Ensure customer success with seamless IP integration. Enhance team collaboration and workflow.
\nBS/MS/PhD in Electronics Engineering or related field. 6+ years in design verification. Experience with VCS/Verdi and formal verification tools. Knowledge of UPF, UVM, SVA is a plus. Debugging and Perl/TCL/Python scripting skills.
\nResponsible, results-driven, and a strong communicator. Team-oriented and supportive. Self-motivated and enthusiastic about technology.
\nWork with a talented group of engineers developing high-performance IP for cutting-edge applications, in a collaborative and inclusive environment.
\nWe offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details during the hiring process.
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\nYour key responsibilities will include working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP. You will plan tests, checklists, coverage, and assertion planning. You will create detailed verification environments from functional specifications. You will apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. You will write test cases, checkers, and coverage that implement the verification test plan. You will debug simulations, including those of real signals modeled using SystemVerilog for analog. You will perform RTL, GLS, and co-simulations and ensure coverage closure. You will participate in technical reviews and contribute actively. You will provide customer support with the bring-up of IP in customer simulation environments. You will follow and improve development processes to ensure high-quality output.
\nTo be successful in this role, you will need a BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. You will require 2+ years of experience in design verification. You will need strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. You will require proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.
\nAs a highly responsible and result-oriented individual, you will excel in this role if you have excellent English communication skills, both verbal and written. You will be a great team player, willing to support others. You will be self-motivated and highly enthusiastic about technology and solving problems.
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\nAs a Digital Verification Sr Engineer, you will be responsible for working in a collaborative environment to develop and validate complex digital mixed signals for high-speed interface IP.
\nKey responsibilities include:\nPlanning tests, checklists, coverage, and assertion planning.\nCreating detailed verification environments from functional specifications.\nApplying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.\nWriting test cases, checkers, and coverage that implement the verification test plan.\nDebugging simulations, including those of real signals modeled using SystemVerilog for analog.\nPerforming RTL, GLS, and co-simulations and ensuring coverage closure.\nParticipating in technical reviews and contributing actively.\nProviding customer support with the bring-up of IP in customer simulation environments.\nFollowing and improving development processes to ensure high-quality output.
\nRequirements include:\nBS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.\n2+ years of experience in design verification.\nStrong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal).\nKnowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus.\nProficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.
\nIdeal candidate will be highly responsible and result-oriented, with excellent English communication skills, both verbal and written.\nA great team player, willing to support others.\nSelf-motivated and highly enthusiastic about technology and solving problems.
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\nWhat you'll do
\nWhat you need
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