These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are hiring a Staff Engineer to lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.

As a Staff Engineer, you will be responsible for leading the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies. You will work on hands-on execution of layout development, ensuring precision and adherence to industry standards.

You will also mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.

Estimating project efforts, planning schedules, and executing projects in cross-functional settings will be another key responsibility.

Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks will also be a part of your role.

Managing the release process, ensuring timely delivery and consistent quality of layout deliverables will be your additional responsibility.

Key Responsibilities:

• Lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.

• Hands-on execution of layout development, ensuring precision and adherence to industry standards.

• Mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.

• Estimating project efforts, planning schedules, and executing projects in cross-functional settings.

• Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.

• Managing the release process, ensuring timely delivery and consistent quality of layout deliverables.

Requirements:

• BTech/MTech degree in Electrical Engineering, Electronics, or related field.

• 5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).

• Expertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.

• Strong understanding of floorplan techniques and deep submicron effects.

• Proven ability to lead projects and deliver best product quality within tight timelines.

Preferred Qualifications:

• Collaborative and team-oriented, with a commitment to inclusion and diversity.

• Detail-oriented, with strong problem-solving and analytical skills.

• Effective communicator, both written and verbal, with excellent interpersonal abilities.

• Adaptable and eager to learn, embracing new technologies and methodologies.

• Empathetic mentor, fostering accountability, ownership, and technical growth in others.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.

• In addition to company holidays, we have ETO and FTO Programs.

• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Save for your future with our retirement plans that vary by region and country.

• Competitive salaries.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a visionary leader and seasoned layout design professional, passionate about advancing the frontiers of semiconductor technology. With over eight years of hands-on experience, you thrive in dynamic environments where innovation and technical excellence are paramount.

You possess a deep understanding of deep submicron effects, advanced floorplanning techniques, and process technologies like CMOS, FinFET, and GAA at 7nm and below. Your expertise extends to layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, and IO frame and pitch requirements.

You are adept at leading multi-disciplinary teams, creating an environment of accountability, ownership, and growth, while mentoring junior engineers and empowering senior team members to excel.

You value diversity and inclusion, fostering a culture where every voice is heard and respected. Your collaborative approach ensures seamless cross-functional coordination, and you have a knack for translating complex technical requirements into actionable project plans.

Your communication skills,both written and verbal,enable you to engage effectively with stakeholders at all levels. You are motivated by the opportunity to contribute to high-impact projects, drive innovation in DDR/HBM PHY IP layout, and deliver differentiated products that shape the industry.

If you are ready to lead, inspire, and make a lasting impact, Synopsys is the place for you.

Leading the development of next-generation DDR/HBM IP layouts, driving technical innovation and quality excellence.

Mentoring and managing a team of layout engineers, fostering growth and maximizing individual and team potential.

Developing and maintaining project schedules, ensuring timely delivery while balancing technical and resource constraints.

Collaborating cross-functionally with design, verification, and IP teams to align on project requirements and execution.

Providing subject matter expertise in high-speed DDR/HBM IP layout, including floorplanning, layout reviews, and quality checks.

Executing layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO requirement analysis.

Supporting layout automation through scripting and tool enhancement, optimizing efficiency and productivity.

Acting as an advisor to resolve project challenges and guide teams towards innovative solutions.

Accelerating the integration of advanced capabilities into SoCs, helping customers achieve unique performance, power, and size targets.

Reducing time-to-market and risk for differentiated products through robust layout design and technical leadership.

Driving continuous improvement in layout methodologies and quality standards across cross-functional teams.

Empowering your team to deliver high-performance DDR/HBM PHY IPs that set industry benchmarks.

Fostering a collaborative, inclusive work environment that values innovation, accountability, and diversity.

Contributing to Synopsys’ reputation as the provider of the world’s broadest portfolio of silicon IP.

Shaping the future of chip design and verification technologies through your expertise and leadership.

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Responsibilities:

• Manage a team and develop SRAM/Register file /TCAM /ROM architectures and circuit implementation techniques.
• Schematic entry, simulation of major blocks, layout planning, layout supervision and interface with CAD team for full verification and model generation.
• Designing and implementing optimum low-power and area-efficient embedded memory (SRAM, register files, etc.) circuits and architectures.
• Learn and apply skills in memory compilers having Transistor level circuit Design.
• Resolves a wide range of issues in creative ways
• Inter-team interaction
• Customer focus
• Frequently networks with senior internal and external personnel in own area of expertise
• Experience of FinFet Technology for Memory Design
• Can coordinate, facilitate, and monitor the daily activities of a small to large group of support resources within their section or project team
• With minimal supervision, prioritizes workload to successfully manage multiple tasks and responsibilities
• Proactively addresses and communicates issues impacting productivity

As a Manager, the individual will be involved in challenging projects and drive it to completion in record time.

You will quickly ramp on the existing flow, understand the challenges, and produce the work plan.

Your expertise in deep submicron technology and Finfet, SRAM design, processor design, Digital design flow and teamwork skills will be highly leveraged to guide activity across the entire cross-discipline, multi-site team.

You will work with others to identify the issues, get buy-in on proposed solutions, and implement the solutions in time for the team to execute to schedule.

Skills/Experience:

• 10yrs+ Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation.
• BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering from premium institute/university
• Deep understanding of SRAM/Register File architectures and advanced custom circuit implementations.
• Direct experience with the most advanced technology nodes. Familiarity with variation-aware design in nanometre technology nodes
• Mastery in scripting using Perl, python for automation

Fundamentals:

• Understanding of RC circuit of 1st and 2nd order.
• Basics of Digital design (realization of Boolean function using Gates, Mux etc)
• Fundamentals of Transfer function and its analysis for stability etc.
• Strong CMOS fundamentals
• Knowledge of CMOS fabrication
• Good digital design knowledge
• Exposure to basic Analog fundamentals

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

• Health & Wellness: Comprehensive medical and healthcare plans that work for you and your family.
• Time Away: In addition to company holidays, we have ETO and FTO Programs.
• Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Retirement Plans: Save for your future with our retirement plans that vary by region and country.
• Compensation: Competitive salaries.

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As a Sr Staff Engineer in Custom Analog Enablement and Methodology, you will propose and develop advanced layout design techniques and methodologies, including specification, prototyping, and building solutions with scripting languages (Tcl/Perl/Python). You will run verification on existing designs to assess PDK update impacts and create innovative scripts to minimize rework. You will collaborate with multiple organizations and teams across global time zones to ensure the design environment is optimized for IP design teams.

Key responsibilities include:

• Proposing and developing advanced layout design techniques and methodologies
• Running verification on existing designs to assess PDK update impacts
• Creating innovative scripts to minimize rework
• Collaborating with multiple organizations and teams across global time zones

The ideal candidate will have a deep understanding of custom analog layout design, especially with sub-5nm FinFet/Gate-All-Around nodes. You will be proficient in scripting languages: Tcl, Perl, and Python for workflow automation and prototyping. You will also have the ability to debug LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports effectively.

This role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15231

Remote Eligible

No

Date Posted

02/15/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

• An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL , data converters and SERDES design.

• You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction.

• Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes.

• You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology.

• You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation.

• You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution.

What You’ll Be Doing:

• Leading NRZ/PAM4 Serdes analog design transceiver solutions.

• Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.

• Collaborating with silicon test and debug experts for Sim2Sil correlation.

• Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.

The Impact You Will Have:

• Driving innovation in mixed-signal advanced analog serdes design.

• Enhancing the performance and efficiency of high-speed physical interfaces.

• Contributing to the development of cutting-edge technology in High Speed PHY IP.

• Improving quality and robustness of design through collaboration and Sim2Sil correlation.

What You’ll Need:

• BE 15+ years of relevant experience or MTech 12+ years of relevant experience in mixed signal analog, clock, and datapath circuit design.

• Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.

• Knowledge in Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity .

• Knowledge of RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters

Who You Are:

• Strong fundamentals of CMOS, device physics, and sub-micron design methodologies.

• Experience with PLL designs and high-speed digital circuit design.

• Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques.

• Familiarity with digitally assisted analog circuit techniques.

• Capable to drive technical decision and tradeoff with customer focus

The Team You’ll Be A Part Of:

Join our High-Performance Computing (HPC) Enterprise analog/mixed-signal Serdes team involved in cutting-edge High Speed PHYSICAL Interface Development.

You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Defining and deploying advanced layout methodologies that accelerate execution, enhance quality, and promote standardized best practices across global teams.

Gathering customer requirements, translating them into clear technical specifications, and ensuring these specifications drive methodology and workflow development.

Developing end-to-end workflows that enhance quality, consistency, and efficiency across Synopsys IP development.

Collaborating closely with cross-functional teams—including Circuit Design, Physical Design, CAD, Product Engineering, and Quality—to enable adoption of methodologies for advanced technology nodes.

Providing technical leadership across distributed teams, aligning planning and execution to meet project goals.

Defining, tracking, and analyzing performance metrics to drive continuous improvement and influence future methodology strategy.

Creating and maintaining comprehensive documentation to ensure clarity, scalability, and long-term usability.

Engaging with internal partners and external customers as a trusted technical representative of the Methodology Team.

Leading innovation in analog/mixed-signal layout flows, combining industry-standard tools and internal automation to validate and evolve methodologies.

Mentoring and supporting junior engineers, enabling skill growth and knowledge sharing across the organization.

Accelerating and improving the reliability of analog/mixed-signal IP development at advanced nodes.

Driving alignment and quality across global design teams through standardized workflows and strong technical leadership.

Strengthening collaboration and knowledge transfer across engineering disciplines.

Influencing organizational and product strategy through methodology innovation and customer insights.

Increasing transparency and maintainability of workflows through high-quality documentation.

Contributing to reinforcing Synopsys’ position as a leader in semiconductor design technology.

5+ years in analog/mixed-signal layout or ASIC physical design, with experience in FinFET and advanced nodes strongly preferred.

Deep knowledge of analog and mixed-signal CMOS layout, device-level considerations, and chip-level integration.

Strong expertise with industry tools such as Synopsys Custom Compiler, Cadence Virtuoso, ICV, Calibre, and related verification flows.

Proven ability to gather customer requirements and convert them into technical specifications.

Demonstrated experience building workflows that improve IP quality, efficiency, and consistency.

Strong organizational skills, attention to detail, and ability to manage multiple complex initiatives simultaneously.

Excellent communication, leadership, and mentoring abilities.

Innovative and proactive in solving complex engineering challenges.

Collaborative, with a talent for working across interdisciplinary teams.

Strategic thinker who balances technical depth with big-picture vision.

Effective communicator, able to convey technical concepts to diverse audiences.

Mentor and coach, dedicated to supporting the growth of others.

Adaptable and resilient in fast-paced and evolving environments.

You will join the Mixed Signal IP Technology and Methodology Team—an advanced physical design group focused on developing full-custom analog and ASIC layout solutions for high-speed integrated circuits. The team is known for its collaborative culture, cutting-edge tool ecosystem, and strong commitment to innovation. As a Staff Engineer, you’ll work closely with experienced layout engineers, CAD specialists, and circuit designers to help define best-in-class methodologies and deliver high-quality solutions for Synopsys’ global customers.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a visionary and seasoned engineering leader, driven by a passion for innovation in ASIC physical design. Seeking a highly motivated and innovative ASIC Physical Design Implementation Engineer to lead the Test Chip PHY development. You will lead a team of engineers to develop Test Chips for DDR/HBM/UCIe protocols. The position offers an excellent opportunity to work on mixed-signal IPs with a focus on digital design.

What You’ll Be Doing:

Lead Test Chip Physical Design Implementation: Oversee all aspects of physical implementation for test chips, including integration of IP blocks and custom logic for validation purposes. Candidate will lead multiple test chips that will be developed in parallel to tape-out for various foundry shuttles.

Resource & Project Leadership: Lead a team of physical design engineers; allocate resources, schedule tasks, and manage priorities for on-time project execution.

Floor planning & Power Planning: Develop overall floorplan and power/ground strategy tailored for the test chip architecture.

Synthesis to GDSII: Own and drive the entire RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.

Timing Closure: Execute and oversee static timing analysis (STA) for the test chip, ensuring robust timing signoff.

Design Integrity Checks: Conduct and resolve EM/IR drop analysis and physical verification (ERC/DRC/LVS), as well as PERC/ESD analysis specific to test chips.

Block/Chip-level Integration: Integrate updated covercells, circuit/IP/PLL/hard-macros, abutment checking, and QA/review/release of hard-macros.

Tool Flow Enhancements & Debug: Drive tool flow automation and debugging to improve productivity and design reliability.

Collaboration: Work closely with Architecture, FE RTL, Circuit and Covercell teams before and during the TC development

Release & Documentation: Prepare and release all supporting views necessary for the tape out of the test chips on to the foundry portal. File, update and maintain the mask tooling form on the foundry website and fill out the necessary checklists

What You’ll Need:

• 12+ years of proven experience in ASIC physical Design, with expertise in leading complex SoC or test chip implementations at advanced process nodes.
• Deep knowledge of the entire ASIC physical design flow, including floor planning, synthesis, place and route, timing closure, IR-drop/EM analysis, LVS/DRC, and related methodologies.
• Demonstrated experience leading engineering teams and managing cross-functional projects in high-pressure environments.
• Familiarity with test chip methodology, IP integration, and advanced verification flows.
• Proficiency with state-of-the-art CAD tools such as DC, PT, ICC2/FC, ICV, Calibre, RedHawk, and advanced technologies like FinFet.
• Strong communication, problem-solving, and project management skills.

The Impact You Will Have:

• Elevate Synopsys’ leadership in advanced ASIC and IP development by delivering high-performance, reliable test chips.
• Enable rapid validation and integration of DDR/HBM/UCIe protocols, supporting next-generation silicon innovation.
• Enhance cross-functional collaboration, accelerating project timelines and improving overall design quality.
• Drive process improvements through tool flow automation, setting new standards for productivity and design reliability.
• Ensure robust manufacturability and performance, reducing risk and increasing success rates in foundry tape-outs.
• Mentor and develop junior engineers, fostering a culture of technical excellence and continuous learning.
• Contribute to the creation of industry-leading mixed-signal IPs, elevating Synopsys’ portfolio and market position.

Who You Are:

• Innovative thinker with a passion for solving complex engineering challenges.
• Inspirational leader who empowers teams and fosters collaborative, inclusive environments.
• Meticulous and detail-oriented, committed to quality and design integrity.
• Adaptable and resilient, thriving in fast-paced, dynamic settings.
• Excellent communicator, able to articulate technical concepts to diverse audiences.
• Continuous learner, eager to stay at the forefront of technology and industry trends.

The Team You’ll Be A Part Of:

You’ll join a highly skilled, multidisciplinary team focused on developing industry-leading test chips for cutting-edge protocols like DDR, HBM, and UCIe. The team values collaboration, innovation, and technical excellence, working closely with architecture, RTL, circuit, and verification experts to deliver best-in-class mixed-signal IP solutions. Together, you’ll shape the next generation of silicon technology and drive Synopsys’ continued success in the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#LI-NK4

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

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Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our 401(k) and 401(k) matching program.

• ### Other Benefits

Flexible work arrangements, employee discounts, and more.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15391

Remote Eligible

No

Date Posted

02/23/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ & PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.

You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.

Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.

What You’ll Be Doing:

• Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.

• Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.

• Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.

• Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.

• Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.

• Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.

• Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.

The Impact You Will Have:

• Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.

• Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.

• Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.

• Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.

• Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.

• Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.

What You’ll Need:

• MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).

• Proven expertise with FinFET technologies and CMOS tape-outs.

• Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.

• Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).

• Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.

• Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).

• Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.

• Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.

• Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).

• Excellent communication and documentation skills.

Who You Are:

• Collaborative and open-minded, eager to share knowledge and learn from others.

• Detail-oriented and thorough, with a commitment to delivering high-quality results.

• Analytical thinker with strong problem-solving abilities and a proactive approach.

• Excellent communicator, able to convey complex technical concepts clearly.

• Adaptable and resilient in fast-paced, dynamic environments.

• Committed to fostering an inclusive, innovative, and supportive workplace.

The Team You’ll Be A Part Of:

You’ll join a world-class analog and mixed-signal R&D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What is it like to be an Analog Design Engineer at Synopsys?

Arman Shahmuradyan

Analog Design, Manager

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and patern

XML job scraping automation by YubHub

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are: You are a passionate and inventive analog circuit design engineer with a deep-rooted curiosity for emerging technologies and industry-leading semiconductor processes. You thrive in dynamic, collaborative environments and are recognised for your ability to balance technical depth with practical implementation.

Responsibilities: Designing and developing best-in-class ESD and Latch-Up robust solutions for advanced interface IPs using cutting-edge FinFet, FDSOI, and BCD processes. Owning the full lifecycle of ESD structures—from schematic design, simulation, and layout to silicon qualification and production release. Leading and executing I/O development, including I/O ring design, review, and optimisation for performance and robustness. Developing and qualifying Interface Testchips, ensuring comprehensive ESD and Latch-Up validation to meet global customer requirements. Running ESD simulations by building detailed ESD networks and performing advanced analyses to ensure design integrity. Applying foundry-provided PERC (Physical Verification Rule Check) rules and using PERC check tools to validate compliance and enhance design quality. Collaborating closely with foundry partners, design, and layout teams to ensure timely and effective integration of ESD and LU solutions.

The Impact You Will Have: Elevating the reliability and performance of Synopsys' interface IPs, directly influencing the success of global semiconductor customers. Driving innovation in analog circuit design for next-generation silicon technologies, helping Synopsys maintain its leadership in the industry. Reducing field failures and increasing product longevity by delivering robust ESD and Latch-Up protection solutions. Accelerating time-to-market for customer products through efficient and high-quality design practices. Fostering a culture of technical excellence and continuous improvement within the analog design team. Building strong partnerships with foundries and cross-functional teams, enhancing collaboration and knowledge sharing across projects.

What You’ll Need: Proven experience in analog circuit design, with a focus on I/O development and ESD/LU robustness. Hands-on expertise with FinFet, FDSOI, and BCD process technologies from leading foundries. Strong background in ESD and Latch-Up qualification methodologies, including testchip development and validation. Proficiency in ESD simulation, ESD network construction, and use of industry-standard tools. Comprehensive understanding of PERC rules and practical experience with PERC verification tools. Experience working with cross-functional teams including foundry, design, and layout groups.

Who You Are: An analytical thinker with excellent problem-solving skills and keen attention to detail. A collaborative team player who values diversity, inclusion, and open communication. A proactive learner who stays current with industry trends and emerging technologies. An effective communicator, able to translate complex technical information to diverse audiences. A results-driven individual who is adaptable, resilient, and comfortable with fast-paced, high-impact work.

The Team You’ll Be A Part Of: You’ll join a passionate, multidisciplinary team of analog and mixed-signal engineers dedicated to advancing Synopsys’ interface IP portfolio. The team is focused on delivering robust, innovative, and high-quality solutions that meet the rigorous demands of a global customer base. Collaboration, continuous improvement, and technical mentorship are at the core of our culture, ensuring you’ll have the support and opportunities needed to thrive and grow.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What you'll do

• Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment.
• Collaborate with cross-functional teams to ensure successful project execution.
• Create and review layout documents to ensure they meet quality standards and are delivered on time.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Minimum 3+ years of experience in Analog and Mixed Signal Circuit Layout.

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What you'll do

• Designing and integrating memory leafcells and standard cell layouts.
• Optimizing layouts for speed, area, and power.
• Running and debugging DRC, LVS, and ERC checks.
• Collaborating with circuit and verification engineers.

What you need

• 2+ years in custom, standard cell, or memory layout design.
• Experience with FinFET, DRC, LVS, ERC, and boundary conditions.
• Proficiency in Custom Compiler, ICV, and scripting (Perl, Shell, TCL).

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What you'll do

Designing and verifying embedded memory compilers for advanced nodes. Collaborating with layout, methodology, and testchip teams to solve technical issues. Optimizing memory architectures for performance and efficiency. Using spice simulators for circuit validation. Communicating technical updates effectively.

What you need

• Expertise in embedded memory (SRAM/ROM/RF/TCAM) design.
• Experience with FinFET/advanced technologies.
• Proficiency with spice simulators and schematic architecture.
• Strong technical communication in Vietnamese and English.
• Team collaboration skills.

Why this matters

Accelerate delivery of high-performance memory IP. Drive innovation in Foundation IP Group projects. Enable cutting-edge chip designs for global clients. Support team collaboration and technical excellence.

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What you'll do

Review SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.

Investigate and architect circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.

Collaborate with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.

Oversee and guide the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.

Present and review simulation data with internal teams and external stakeholders, including industry panels and customer reviews.

Document design features, test plans, and results, and consult on electrical characterization and post-silicon analysis for product enhancements.

Analyze customer silicon data to identify design improvement opportunities and propose solutions for post-silicon updates.

What you need

MTech/MS with 7+ years or BTech/BS with 8+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).

Proven expertise with FinFET technologies and CMOS tape-outs.

Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.

Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).

Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.

Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).

Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.

Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.

Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).

Excellent communication and documentation skills.

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What you'll do

You will lead the NVM TestChip and IP design flow across multiple technologies and foundries, ensuring robust and scalable solutions for diverse applications.

• Architecting, designing, and verifying CMOS-based non-volatile memory IP modules, from concept to production tapeout.
• Collaborating with product engineers to perform silicon verification, in-depth testing, and debugging to validate IP performance on silicon.
• Conducting post-layout extraction, simulation, and comprehensive testing in conjunction with silicon validation teams.

What you need

• 5–12+ years of industry experience in circuit design, with a strong emphasis on analog circuit design and analysis; memory design experience is a significant plus.
• Deep understanding of layout considerations for advanced nodes, including parasitic effects, matching techniques, and signal integrity.
• Expertise in electrical problem-solving, including root cause analysis of circuit failures and development of effective solutions.
• Hands-on experience with TestChip tapeout flows, silicon debugging (FIB, micro-probing, post-layout RC extraction), and statistical design methodologies (e.g., Monte-Carlo analysis).
• Strong transistor-level analog design skills, including sense-amplifier, charge pump, high voltage regulator, and bandgap reference circuit design.
• Proficiency with circuit simulation tools (HSIM, HSPICE, etc.) and custom schematic/layout editors (e.g., Custom Compiler).
• Experience with low power design, power management circuitry, and FinFET design is a plus.

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What you'll do

Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment.

• Collaborate with cross-functional teams to ensure successful project execution.

• Create and review layout documents to ensure they meet quality standards and are delivered on time.

What you need

Bachelor's or Master's degree in Electrical Engineering or a related field.

• Minimum 9+ years of experience in Analog and Mixed Signal Circuit Layout.

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