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As a senior-level engineer, you&#39;ll design, build, and optimise the core systems and management platforms that power the Instabase platform.</p>\n<p>This is a high-impact role for a &#39;product-minded engineer&#39;. In our Core Services team, we treat our platform as a product. Because we operate with a lean team, you will have end-to-end ownership: from writing Product Requirement Documents (PRDs) and building the high-performance backend services and scalable infrastructure that support them.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Full Stack Development: You will function as a product-minded engineer for our internal platform. This involves architecting secure infrastructure (Kubernetes, Docker) and backend services (Go, Python, PostgresDB), while also building the frontend interfaces (React, TS) to support features.</li>\n</ul>\n<ul>\n<li>Developer Experience: Create the internal platforms and dashboards that improve developer velocity, reliability, and observability across the entire organisation.</li>\n</ul>\n<ul>\n<li>Technical Leadership: Act as a technical leader who mentors junior engineers, contributes to the entire infrastructure codebase, and identifies root causes for critical system issues.</li>\n</ul>\n<p>About you:</p>\n<ul>\n<li>Education: BS, MS, or PhD in Computer Science, or equivalent experience in a technical field such as Physics or Mathematics.</li>\n</ul>\n<ul>\n<li>Experience: 5+ years of professional software development experience with a strong foundation in CS fundamentals.</li>\n</ul>\n<ul>\n<li>Backend Expertise: Proficiency in Go and Python, with a deep understanding of building scalable backend services and APIs.</li>\n</ul>\n<ul>\n<li>Frontend Expertise: Strong experience with React, TypeScript, and JavaScript for building complex, data-rich web applications.</li>\n</ul>\n<ul>\n<li>Infrastructure &amp; Orchestration: Proficiency with Docker, Kubernetes, and cloud infrastructure (AWS, GCP, or Azure).</li>\n</ul>\n<ul>\n<li>Product Thinking &amp; UI Design: You are comfortable functioning as your own PM and Designer and write technical specs (PRDs) to define how users interact with infrastructure.</li>\n</ul>\n<ul>\n<li>Communication: Excellent communication skills to represent technical and product decisions to the wider engineering team.</li>\n</ul>\n<p>Good to have:</p>\n<ul>\n<li>Experience with React Native for mobile or cross-platform applications.</li>\n</ul>\n<ul>\n<li>Prior experience in a startup environment where you handled multi-functional responsibilities (Dev, PM, and Design).</li>\n</ul>\n<p>Compensation: The base salary range for this role is $190,000 to $205,000 + bonus, equity and US benefits.</p>\n<p>US Benefits:</p>\n<ul>\n<li>Flexible PTO: Because life is better when you actually live it!</li>\n</ul>\n<ul>\n<li>Comprehensive Coverage: Top-notch medical, dental, and vision insurance.</li>\n</ul>\n<ul>\n<li>401(k) with Matching: We’ve got your back for a secure future.</li>\n</ul>\n<ul>\n<li>Parental Leave &amp; Fertility Benefits: Supporting you in growing your family, your way.</li>\n</ul>\n<ul>\n<li>Therapy Sessions Covered: Mental health matters, 10 free sessions through Samata Health.</li>\n</ul>\n<ul>\n<li>Wellness Stipend: For gym memberships, fitness tech, or whatever keeps you thriving.</li>\n</ul>\n<ul>\n<li>Lunch on Us: Enjoy a lunch credit when you&#39;re in the office.</li>\n</ul>\n<p>#LI-Hybrid</p>\n<p>Instabase is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender perception or identity, national origin, age, marital status, protected veteran status, or disability status.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_bc54ed6c-ca0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Instabase","sameAs":"https://www.instabase.com/","logo":"https://logos.yubhub.co/instabase.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/instabase/jobs/8186577002","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$190,000 to $205,000 + bonus, equity and US benefits","x-skills-required":["Go","Python","PostgresDB","Kubernetes","Docker","React","TypeScript","JavaScript","Cloud infrastructure (AWS, GCP, or Azure)"],"x-skills-preferred":[],"datePosted":"2026-04-18T15:53:35.809Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco, CA"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Go, Python, PostgresDB, Kubernetes, Docker, React, TypeScript, JavaScript, Cloud infrastructure (AWS, GCP, or Azure)","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":190000,"maxValue":205000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_0937c3cd-bd3"},"title":"Software Engineer Intern","description":"<p>We&#39;re looking for a Software Engineering Intern to join our team for a 10-week summer program. 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Actual compensation offered will be based on factors such as your work location, qualifications, skills, experience, and/or training.</p>\n<p>We offer comprehensive benefits and holistic mind, body, and lifestyle programs designed for overall well-being. Learn more about our benefits here.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_0937c3cd-bd3","directApply":true,"hiringOrganization":{"@type":"Organization","name":"ZoomInfo","sameAs":"https://www.zoominfo.com/","logo":"https://logos.yubhub.co/zoominfo.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/zoominfo/jobs/8373259002","x-work-arrangement":"hybrid","x-experience-level":"entry","x-job-type":"internship","x-salary-range":"$30-35 per hour","x-skills-required":["strong programming fundamentals","clear communication","strong problem-solving ability","ability to commute to Bethesda, MD or Waltham, MA","commitment to the program for the full 10 weeks"],"x-skills-preferred":[],"datePosted":"2026-04-18T15:53:27.817Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bethesda, Maryland, United States; Waltham, Massachusetts, United States"}},"employmentType":"INTERN","occupationalCategory":"Engineering","industry":"Technology","skills":"strong programming fundamentals, clear communication, strong problem-solving ability, ability to commute to Bethesda, MD or Waltham, MA, commitment to the program for the full 10 weeks"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1a6899d5-2cc"},"title":"ATP Technician Specialist","description":"<p>We are looking for an ATP Technician Specialist to join our rapidly growing team in Costa Mesa, CA. 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They will maintain accurate records of repairs, testing results, and parts usage in compliance with organisational and regulatory standards.</p>\n<p>The ideal candidate will have a high school diploma or equivalent, previous experience as an LRU technician or in a similar role, and proficient knowledge of electronic, electrical, and mechanical systems related to LRUs.</p>\n<p>Preferred qualifications include experience with automated test equipment (ATE) and calibration procedures, knowledge of IPC standards and electrostatic discharge (ESD) safety practices, basic soldering and assembly skills, and familiarity with LRU tracking and inventory management systems.</p>\n<p>The salary range for this role is $28-$38 USD per hour, and the company offers a comprehensive benefits package, including healthcare benefits, income protection, generous time off, family planning and parenting support, mental health resources, professional development opportunities, commuter benefits, relocation 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handling and working with PCBAs\nComposite assembly skills including basic layup procedures, bonding, vacuum bagging, running cure cycles, etc.\nEngine assembly, disassembly, and integration\nFamiliarity with aerospace-specific components such as MIL-SPEC connectors, backshells, braiding, and shielding.\nExperience with quality standards like IPC/WHMA-A-620 Class 3, AS9100, and MIL-STD requirements.</p>\n</li>\n<li><p>Attention to Detail and Precision:\nAbility to work with tight tolerances and ensure 100% quality in all wire harness assemblies.\nStrong problem-solving skills for identifying and addressing manufacturing defects.</p>\n</li>\n<li><p>Certifications:\nIPC/WHMA-A-620 Certification required or willingness to obtain.\nCertification in soldering to J-STD-001 standards preferred.</p>\n</li>\n<li><p>Physical Requirements:\nAbility to work with small components, perform repetitive tasks, and sit or stand for extended periods.\nGood manual dexterity and hand-eye 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Our team collaborates closely with colleagues in Vietnam, USA, Canada, and other countries to ensure the success of our products. We value teamwork, knowledge sharing, and continuous improvement, and we are committed to fostering a supportive and inclusive work environment.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_63c3f231-21b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/analog-layout-design-sr-engineer/44408/92879619712","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Cadence","Synopsys","Mentor Calibre","Synopsys ICV","Electronics Engineering","Electromechanics","Telecommunications","High-speed layout techniques","ESD","Latchup","Antenna","EMIR"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:34.005Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Cadence, Synopsys, Mentor Calibre, Synopsys ICV, Electronics Engineering, Electromechanics, Telecommunications, High-speed layout techniques, ESD, Latchup, Antenna, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_471316cf-932"},"title":"Analog Layout, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are hiring a Staff Engineer to lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.</p>\n<p>As a Staff Engineer, you will be responsible for leading the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies. You will work on hands-on execution of layout development, ensuring precision and adherence to industry standards.</p>\n<p>You will also mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.</p>\n<p>Estimating project efforts, planning schedules, and executing projects in cross-functional settings will be another key responsibility.</p>\n<p>Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks will also be a part of your role.</p>\n<p>Managing the release process, ensuring timely delivery and consistent quality of layout deliverables will be your additional responsibility.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li><p>Lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.</p>\n</li>\n<li><p>Hands-on execution of layout development, ensuring precision and adherence to industry standards.</p>\n</li>\n<li><p>Mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.</p>\n</li>\n<li><p>Estimating project efforts, planning schedules, and executing projects in cross-functional settings.</p>\n</li>\n<li><p>Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.</p>\n</li>\n<li><p>Managing the release process, ensuring timely delivery and consistent quality of layout deliverables.</p>\n</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li><p>BTech/MTech degree in Electrical Engineering, Electronics, or related field.</p>\n</li>\n<li><p>5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).</p>\n</li>\n<li><p>Expertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.</p>\n</li>\n<li><p>Strong understanding of floorplan techniques and deep submicron effects.</p>\n</li>\n<li><p>Proven ability to lead projects and deliver best product quality within tight timelines.</p>\n</li>\n</ul>\n<p>Preferred Qualifications:</p>\n<ul>\n<li><p>Collaborative and team-oriented, with a commitment to inclusion and diversity.</p>\n</li>\n<li><p>Detail-oriented, with strong problem-solving and analytical skills.</p>\n</li>\n<li><p>Effective communicator, both written and verbal, with excellent interpersonal abilities.</p>\n</li>\n<li><p>Adaptable and eager to learn, embracing new technologies and methodologies.</p>\n</li>\n<li><p>Empathetic mentor, fostering accountability, ownership, and technical growth in others.</p>\n</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li><p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n</li>\n<li><p>In addition to company holidays, we have ETO and FTO Programs.</p>\n</li>\n<li><p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n</li>\n<li><p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n</li>\n<li><p>Save for your future with our retirement plans that vary by region and country.</p>\n</li>\n<li><p>Competitive salaries.</p>\n</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_471316cf-932","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/analog-layout-staff-engineer/44408/92693931728","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","CMOS","FinFET","GAA process technologies","layout matching techniques","ESD","latch-up","PERC","EMIR","DFM","LEF generation","bond-pad layout","IO frame and pitch requirements"],"x-skills-preferred":["collaborative and team-oriented","detail-oriented","effective communicator","adaptable and eager to learn","empathetic mentor"],"datePosted":"2026-04-05T13:21:26.995Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, CMOS, FinFET, GAA process technologies, layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements, collaborative and team-oriented, detail-oriented, effective communicator, adaptable and eager to learn, empathetic mentor"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6eb810f3-99d"},"title":"Layout Design, Staff Engineer-16003","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Layout Design Engineer, you will be designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces. You will collaborate with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces.</li>\n<li>Collaborating with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.</li>\n<li>Performing floor planning, layout entry, and comprehensive verification to ensure design quality and compliance with foundry rules.</li>\n<li>Applying advanced techniques to mitigate signal integrity issues, ESD, and latch-up risks, including differential routing, shielding, and substrate biasing.</li>\n<li>Optimizing layouts for reliability, matching, and minimizing parasitic effects such as EM and IR drop.</li>\n<li>Supporting design porting activities to enable seamless migration of layouts across multiple foundry nodes and technology platforms.</li>\n<li>Documenting layout methodologies, best practices, and validation results to support knowledge sharing and continuous improvement.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor or advanced degree in Electrical or Computer Engineering (or equivalent) with a solid background in transistor-level design.</li>\n<li>5+ years of experience in analog and mixed-signal CMOS layout design, including complex integrated circuits.</li>\n<li>Expertise in deep submicron CMOS technologies and layout effects (matching, reliability, proximity, EM, IR, etc.).</li>\n<li>Proficiency in layout floor planning, verification, and quality validation using industry-standard EDA tools.</li>\n<li>Strong knowledge of signal integrity, ESD, and latch-up mitigation techniques.</li>\n<li>Familiarity with UNIX operating systems and scripting languages (TCL, Python) is a plus.</li>\n<li>Experience with Synopsys EDA tools is highly desirable.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Detail-oriented and quality-focused, with a commitment to delivering robust and reliable designs.</li>\n<li>Excellent communicator, able to articulate technical concepts clearly to diverse audiences.</li>\n<li>Collaborative team player who builds productive relationships and networks effectively.</li>\n<li>Self-motivated, organized, and able to manage multiple priorities in a dynamic environment.</li>\n<li>Strong problem-solving skills and critical judgment, with a proactive approach to overcoming challenges.</li>\n<li>Adaptable and eager to learn new technologies and methodologies.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Accelerate the development of cutting-edge silicon IP, enabling faster integration of advanced capabilities into SoCs.</li>\n<li>Enhance the performance, reliability, and manufacturability of high-speed interface solutions for next-generation applications.</li>\n<li>Reduce time-to-market and risk for customers by delivering high-quality, validated layout designs.</li>\n<li>Contribute to the innovation of analog and mixed-signal design methodologies within a global team.</li>\n<li>Support the creation of differentiated products that power the Era of Smart Everything, from AI to IoT and beyond.</li>\n<li>Foster a culture of collaboration, knowledge sharing, and technical excellence within the team and across the organization.</li>\n</ul>\n<p>The Team You&#39;ll Be A Part Of:</p>\n<p>You will join a dynamic, international team focused on developing high-speed SerDes physical interfaces and supporting analog blocks for advanced SoC solutions. Our team values innovation, collaboration, and technical excellence, working closely with circuit designers, verification engineers, and global partners to deliver industry-leading silicon IP. We foster a supportive environment where knowledge sharing and continuous learning are encouraged, and where your contributions will directly impact the success of our products and customers.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_6eb810f3-99d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ottawa/layout-design-staff-engineer-16003/44408/92625958368","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["CMOS circuit layout","high-speed SerDes physical interfaces","deep submicron CMOS technologies","layout effects","signal integrity","ESD","latch-up mitigation","UNIX operating systems","scripting languages","Synopsys EDA tools"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:26.656Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ottawa"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"CMOS circuit layout, high-speed SerDes physical interfaces, deep submicron CMOS technologies, layout effects, signal integrity, ESD, latch-up mitigation, UNIX operating systems, scripting languages, Synopsys EDA tools"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_41cabece-785"},"title":"Layout Design, Sr Supervisor","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a visionary leader and seasoned layout design professional, passionate about advancing the frontiers of semiconductor technology. With over eight years of hands-on experience, you thrive in dynamic environments where innovation and technical excellence are paramount.</p>\n<p>You possess a deep understanding of deep submicron effects, advanced floorplanning techniques, and process technologies like CMOS, FinFET, and GAA at 7nm and below. Your expertise extends to layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, and IO frame and pitch requirements.</p>\n<p>You are adept at leading multi-disciplinary teams, creating an environment of accountability, ownership, and growth, while mentoring junior engineers and empowering senior team members to excel.</p>\n<p>You value diversity and inclusion, fostering a culture where every voice is heard and respected. Your collaborative approach ensures seamless cross-functional coordination, and you have a knack for translating complex technical requirements into actionable project plans.</p>\n<p>Your communication skills,both written and verbal,enable you to engage effectively with stakeholders at all levels. You are motivated by the opportunity to contribute to high-impact projects, drive innovation in DDR/HBM PHY IP layout, and deliver differentiated products that shape the industry.</p>\n<p>If you are ready to lead, inspire, and make a lasting impact, Synopsys is the place for you.</p>\n<p>Leading the development of next-generation DDR/HBM IP layouts, driving technical innovation and quality excellence.</p>\n<p>Mentoring and managing a team of layout engineers, fostering growth and maximizing individual and team potential.</p>\n<p>Developing and maintaining project schedules, ensuring timely delivery while balancing technical and resource constraints.</p>\n<p>Collaborating cross-functionally with design, verification, and IP teams to align on project requirements and execution.</p>\n<p>Providing subject matter expertise in high-speed DDR/HBM IP layout, including floorplanning, layout reviews, and quality checks.</p>\n<p>Executing layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO requirement analysis.</p>\n<p>Supporting layout automation through scripting and tool enhancement, optimizing efficiency and productivity.</p>\n<p>Acting as an advisor to resolve project challenges and guide teams towards innovative solutions.</p>\n<p>Accelerating the integration of advanced capabilities into SoCs, helping customers achieve unique performance, power, and size targets.</p>\n<p>Reducing time-to-market and risk for differentiated products through robust layout design and technical leadership.</p>\n<p>Driving continuous improvement in layout methodologies and quality standards across cross-functional teams.</p>\n<p>Empowering your team to deliver high-performance DDR/HBM PHY IPs that set industry benchmarks.</p>\n<p>Fostering a collaborative, inclusive work environment that values innovation, accountability, and diversity.</p>\n<p>Contributing to Synopsys’ reputation as the provider of the world’s broadest portfolio of silicon IP.</p>\n<p>Shaping the future of chip design and verification technologies through your expertise and leadership.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_41cabece-785","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-supervisor/44408/93269033008","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["deep submicron effects","advanced floorplanning techniques","CMOS","FinFET","GAA","layout matching","ESD","latch-up","PERC","EMIR","DFM","LEF generation","bond-pad layout","IO frame and pitch requirements"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:15.106Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"deep submicron effects, advanced floorplanning techniques, CMOS, FinFET, GAA, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cc76d9ba-dc2"},"title":"Staff Layout Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a passionate and detail-oriented engineer who thrives in the fast-paced world of advanced semiconductor layout. You possess a deep understanding of analog and mixed-signal CMOS design principles, with a particular focus on high-speed SerDes interfaces. Your expertise is backed by a solid academic foundation and practical experience, enabling you to tackle complex layout challenges with confidence.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Drive layout development for high-speed SerDes physical interfaces and complex analog/mixed-signal CMOS blocks.</li>\n</ul>\n<ul>\n<li>Lead the complete layout design process, including floorplanning, verification, and quality assurance, with a strong emphasis on reliability and manufacturability.</li>\n</ul>\n<ul>\n<li>Port designs across multiple foundry nodes, ensuring optimal performance and compliance with technology-specific requirements.</li>\n</ul>\n<ul>\n<li>Implement advanced techniques for signal integrity, ESD, and latch-up mitigation, such as differential routing, shielding, and biasing.</li>\n</ul>\n<ul>\n<li>Collaborate closely with design, verification, and manufacturing teams to deliver robust and scalable layout solutions.</li>\n</ul>\n<ul>\n<li>Utilize Synopsys EDA tools and scripting languages (TCL, Python) to automate layout tasks and optimize workflow efficiency.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enable Synopsys customers to achieve higher performance and reliability in their silicon designs.</li>\n</ul>\n<ul>\n<li>Accelerate the time-to-market for cutting-edge semiconductor products by delivering high-quality, manufacturable layouts.</li>\n</ul>\n<ul>\n<li>Enhance the robustness and scalability of Synopsys IP through meticulous attention to detail and innovative design solutions.</li>\n</ul>\n<ul>\n<li>Drive advancements in deep submicron CMOS technology adoption and integration.</li>\n</ul>\n<ul>\n<li>Foster a collaborative environment that supports knowledge sharing, mentorship, and professional growth.</li>\n</ul>\n<ul>\n<li>Support Synopsys’ leadership in chip design and verification by contributing to the development of industry-leading IP blocks.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>MSc in Electrical/Computer Engineering (or equivalent).</li>\n</ul>\n<ul>\n<li>Minimum 3 years hands-on experience in analog and mixed-signal CMOS layout, including high-speed SerDes interfaces.</li>\n</ul>\n<ul>\n<li>Deep knowledge of deep submicron CMOS technologies and design for reliability (EM/IR, matching, proximity effects).</li>\n</ul>\n<ul>\n<li>Proficiency in layout floorplanning, porting designs across foundry nodes, and implementing signal integrity and ESD mitigation strategies.</li>\n</ul>\n<ul>\n<li>Experience with custom digital and high-speed digital layout, as well as Synopsys EDA tools.</li>\n</ul>\n<ul>\n<li>Strong skills in UNIX environments, including shell scripting and command-line operations.</li>\n</ul>\n<ul>\n<li>Familiarity with scripting languages such as TCL and Python.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Excellent problem-solving, organizational, and communication skills.</li>\n</ul>\n<ul>\n<li>Self-motivated and proactive, with the ability to work independently and as part of a team.</li>\n</ul>\n<ul>\n<li>Effective collaborator who values diverse perspectives and fosters inclusive teamwork.</li>\n</ul>\n<ul>\n<li>Adaptable and open to new challenges, with a commitment to continuous improvement.</li>\n</ul>\n<ul>\n<li>Detail-oriented with a strong sense of ownership and pride in delivering high-quality work.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a dynamic, highly skilled team dedicated to developing world-class analog and mixed-signal IP for Synopsys’ global customer base. The team is focused on pushing the boundaries of high-speed interface design, reliability, and manufacturability, working together to solve complex challenges and deliver industry-leading solutions.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cc76d9ba-dc2","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/staff-layout-design-engineer/44408/93269033040","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["MSc in Electrical/Computer Engineering","Analog and mixed-signal CMOS layout","High-speed SerDes interfaces","Deep submicron CMOS technologies","Design for reliability","Layout floorplanning","Porting designs across foundry nodes","Signal integrity and ESD mitigation strategies","Custom digital and high-speed digital layout","Synopsys EDA tools","UNIX environments","Shell scripting and command-line operations","Scripting languages such as TCL and Python"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:06.360Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"MSc in Electrical/Computer Engineering, Analog and mixed-signal CMOS layout, High-speed SerDes interfaces, Deep submicron CMOS technologies, Design for reliability, Layout floorplanning, Porting designs across foundry nodes, Signal integrity and ESD mitigation strategies, Custom digital and high-speed digital layout, Synopsys EDA tools, UNIX environments, Shell scripting and command-line operations, Scripting languages such as TCL and Python"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e14d730c-676"},"title":"Analog Design, Staff Engineer - SERDES","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p><em>big_They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</em></p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a Staff Engineer in our Analog Design team, you will be responsible for designing and developing full custom analog circuit macros for high-speed SERDES PHY IP.</p>\n<p>Your responsibilities will include designing and developing full custom analog circuit macros for high-speed SERDES PHY IP, including transceivers, voltage/current-mode drivers, PLLs, DLLs, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers/deserializers, VCOs, phase interpolators, bandgap references, and clock data recovery circuits.</p>\n<p>You will also collaborate with cross-functional teams locally and globally to refine circuit implementations and achieve optimal power, area, and performance targets.</p>\n<p>In addition, you will ensure analog sub-block performance adheres to SerDes standards and architecture specification documents.</p>\n<p>You will lead verification strategies using advanced simulator features to guarantee the highest quality design outcomes.</p>\n<p>You will oversee physical layout processes to minimize parasitic effects, device stress, and process variations.</p>\n<p>You will present simulation data for peer and customer reviews, and document design features and test plans.</p>\n<p>You will consult on electrical characterization and support the integration of your circuit within the SerDes IP product.</p>\n<p>You will handcraft high-performance clock and data paths using digital/CMOS logic cells and verify timing margins with SPICE and STA tools.</p>\n<p>You will address ESD and latch-up design verification, crosstalk coupling impacts, and ensure robust mixed-signal analog design.</p>\n<p>The impact you will have includes accelerating development of high-performance silicon chips critical to emerging technologies like AI, IoT, and 5G.</p>\n<p>You will optimize chip designs for power, cost, and performance, helping customers reduce project schedules by months.</p>\n<p>You will advance Synopsys&#39; leadership in high-speed interface IP and mixed-signal design innovation.</p>\n<p>You will contribute to the creation of next-generation processes and models for manufacturing advanced chips.</p>\n<p>You will support global collaboration, knowledge sharing, and technical excellence across teams and sites.</p>\n<p>You will enhance customer satisfaction by delivering reliable, scalable, and high-quality analog IP solutions.</p>\n<p>You will drive technical best practices and mentor junior engineers, strengthening the team&#39;s capabilities.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e14d730c-676","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/analog-design-staff-engineer-serdes/44408/93198373952","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog transistor-level circuit design","nanometer technologies","mixed-signal analog circuit design","physical layout optimization","SPICE simulation","static timing analysis (STA)","digital/CMOS logic cells","high-performance datapath design","ESD/latch-up design verification","crosstalk coupling analysis"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:53.313Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog transistor-level circuit design, nanometer technologies, mixed-signal analog circuit design, physical layout optimization, SPICE simulation, static timing analysis (STA), digital/CMOS logic cells, high-performance datapath design, ESD/latch-up design verification, crosstalk coupling analysis"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_0b3b891d-187"},"title":"Analog Design, Principal Engineer","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are an experienced Analog Design Manager with a passion for high-speed SerDes technology. You have a proven track record in leading teams to develop cutting-edge analog integrated circuits. Your expertise in Multi-Gbps NRZ &amp; PAM4 SERDES IP, combined with your strong leadership skills, enables you to guide a team through complex design challenges. You thrive in a collaborative environment, working alongside analog and digital designers from diverse backgrounds. Your technical proficiency is complemented by your ability to develop schedules and action plans that ensure project success. With excellent communication and documentation skills, you effectively present design activities and solutions to critical issues. You are committed to fostering an environment of continuous improvement and operational excellence.</p>\n<p>What You’ll Be Doing:</p>\n<p>Directing and guiding the activities of a team of analog designers developing high-speed SERDES IP.\nConducting design reviews and evaluating the final results of simulation and electrical characterization reports.\nPresenting the results of design activities, technology assessments, or critical issue investigations and making recommendations for actions necessary to achieve desired results.\nSelecting, developing, and evaluating personnel to ensure the efficient operation of the team.\nDeveloping schedules and action plans to meet overall project timelines.\nReviewing documented design features and test plans.\nEnsuring that the team follows processes and operational policies for maximum design quality.\nConsulting on the electrical characterization of the SerDes IP product and proposing solutions for post-silicon design updates.</p>\n<p>What You’ll Need:</p>\n<p>B.Tech/BE/M.Tech/MS in Electronics Engineering.\n8+ years of experience in Analog Design for High-Speed SerDes applications.\n3-5 years of experience in a management or supervisory role.\nIn-depth familiarity with transistor level circuit design and sound CMOS design fundamentals.\nDetailed design experience with SerDes sub-circuits such as receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers,voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, and DAC, DSP, Signal Integrity\nFamiliarity with both analog and digital circuits and issues related to interfacing and timing between them.\nAware of ESD issues (i.e. circuit techniques, layout).\nFamiliarity with custom digital design (i.e. highspeed logic paths).\nKnowledge of design for reliability (i.e. EM, IR, aging, etc.).\nKnowledge of layout effects (i.e. matching, reliability, proximity effects, etc.).\nGood communication and documentation skills.</p>\n<p>The Impact You Will Have:</p>\n<p>Driving the development of high-speed SerDes IP that meets industry standards and customer requirements.\nFostering innovation and excellence within the analog design team.\nEnsuring the delivery of high-quality, reliable analog integrated circuits.\nContributing to the advancement of Synopsys&#39; technology portfolio in the analog and mixed-signal domains.\nEnhancing the performance and efficiency of our high-speed communication products.\nSupporting the growth and development of team members through effective leadership and mentorship.</p>\n<p>Who You Are:</p>\n<p>You are a proactive leader with a strong technical background in analog design. You possess excellent problem-solving skills and the ability to make sound decisions under pressure. Your collaborative nature allows you to work effectively with cross-functional teams. You are detail-oriented and have a keen eye for quality. Your passion for continuous learning and improvement drives you to stay updated with the latest industry trends and technologies. You are committed to fostering a positive and inclusive team culture, encouraging innovation and excellence.</p>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will be part of a fast-growing analog and mixed-signal R&amp;D team developing high-speed analog integrated circuits in the latest FinFET process nodes. The team is composed of talented analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_0b3b891d-187","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/mississauga/analog-design-principal-engineer-14131/44408/91386421616","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Analog Design","High-Speed SerDes Technology","Multi-Gbps NRZ & PAM4 SERDES IP","Transistor Level Circuit Design","CMOS Design Fundamentals","SerDes Sub-Circuits","ESD Issues","Custom Digital Design","Design for Reliability","Layout Effects"],"x-skills-preferred":["Leadership","Communication","Documentation","Problem-Solving","Decision-Making","Collaboration","Quality Assurance","Continuous Learning","Innovation","Excellence"],"datePosted":"2026-04-05T13:18:01.010Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mississauga"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Analog Design, High-Speed SerDes Technology, Multi-Gbps NRZ & PAM4 SERDES IP, Transistor Level Circuit Design, CMOS Design Fundamentals, SerDes Sub-Circuits, ESD Issues, Custom Digital Design, Design for Reliability, Layout Effects, Leadership, Communication, Documentation, Problem-Solving, Decision-Making, Collaboration, Quality Assurance, Continuous Learning, Innovation, Excellence"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5f4e85a9-296"},"title":"Staff Analog Design Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15391</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/23/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ &amp; PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.</p>\n<p>You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.</p>\n<p>Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.</li>\n</ul>\n<ul>\n<li>Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.</li>\n</ul>\n<ul>\n<li>Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.</li>\n</ul>\n<ul>\n<li>Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.</li>\n</ul>\n<ul>\n<li>Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.</li>\n</ul>\n<ul>\n<li>Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.</li>\n</ul>\n<ul>\n<li>Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.</li>\n</ul>\n<ul>\n<li>Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.</li>\n</ul>\n<ul>\n<li>Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.</li>\n</ul>\n<ul>\n<li>Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.</li>\n</ul>\n<ul>\n<li>Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.</li>\n</ul>\n<ul>\n<li>Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).</li>\n</ul>\n<ul>\n<li>Proven expertise with FinFET technologies and CMOS tape-outs.</li>\n</ul>\n<ul>\n<li>Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.</li>\n</ul>\n<ul>\n<li>Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).</li>\n</ul>\n<ul>\n<li>Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.</li>\n</ul>\n<ul>\n<li>Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).</li>\n</ul>\n<ul>\n<li>Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.</li>\n</ul>\n<ul>\n<li>Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.</li>\n</ul>\n<ul>\n<li>Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).</li>\n</ul>\n<ul>\n<li>Excellent communication and documentation skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative and open-minded, eager to share knowledge and learn from others.</li>\n</ul>\n<ul>\n<li>Detail-oriented and thorough, with a commitment to delivering high-quality results.</li>\n</ul>\n<ul>\n<li>Analytical thinker with strong problem-solving abilities and a proactive approach.</li>\n</ul>\n<ul>\n<li>Excellent communicator, able to convey complex technical concepts clearly.</li>\n</ul>\n<ul>\n<li>Adaptable and resilient in fast-paced, dynamic environments.</li>\n</ul>\n<ul>\n<li>Committed to fostering an inclusive, innovative, and supportive workplace.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a world-class analog and mixed-signal R&amp;D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>What is it like to be an Analog Design Engineer at Synopsys?</p>\n<p>Arman Shahmuradyan</p>\n<p>Analog Design, Manager</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and patern</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5f4e85a9-296","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/staff-analog-design-engineer/44408/92076328848","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog IC design","FinFET technologies","CMOS tape-outs","Multi-Gbps high-speed designs","SERDES architectures","analog/digital co-design","calibration","adaptation","timing handoff","ESD protection","custom digital design","design for reliability","schematic entry","physical layout","design verification tools","SPICE simulators","scripting languages","system-level budgeting","signal integrity"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:05:32.632Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad, Telangana, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog IC design, FinFET technologies, CMOS tape-outs, Multi-Gbps high-speed designs, SERDES architectures, analog/digital co-design, calibration, adaptation, timing handoff, ESD protection, custom digital design, design for reliability, schematic entry, physical layout, design verification tools, SPICE simulators, scripting languages, system-level budgeting, signal integrity"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2f942bce-976"},"title":"Analog Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:\nYou are a passionate and inventive analog circuit design engineer with a deep-rooted curiosity for emerging technologies and industry-leading semiconductor processes. You thrive in dynamic, collaborative environments and are recognised for your ability to balance technical depth with practical implementation.</p>\n<p>Responsibilities:\nDesigning and developing best-in-class ESD and Latch-Up robust solutions for advanced interface IPs using cutting-edge FinFet, FDSOI, and BCD processes.\nOwning the full lifecycle of ESD structures—from schematic design, simulation, and layout to silicon qualification and production release.\nLeading and executing I/O development, including I/O ring design, review, and optimisation for performance and robustness.\nDeveloping and qualifying Interface Testchips, ensuring comprehensive ESD and Latch-Up validation to meet global customer requirements.\nRunning ESD simulations by building detailed ESD networks and performing advanced analyses to ensure design integrity.\nApplying foundry-provided PERC (Physical Verification Rule Check) rules and using PERC check tools to validate compliance and enhance design quality.\nCollaborating closely with foundry partners, design, and layout teams to ensure timely and effective integration of ESD and LU solutions.</p>\n<p>The Impact You Will Have:\nElevating the reliability and performance of Synopsys&#39; interface IPs, directly influencing the success of global semiconductor customers.\nDriving innovation in analog circuit design for next-generation silicon technologies, helping Synopsys maintain its leadership in the industry.\nReducing field failures and increasing product longevity by delivering robust ESD and Latch-Up protection solutions.\nAccelerating time-to-market for customer products through efficient and high-quality design practices.\nFostering a culture of technical excellence and continuous improvement within the analog design team.\nBuilding strong partnerships with foundries and cross-functional teams, enhancing collaboration and knowledge sharing across projects.</p>\n<p>What You’ll Need:\nProven experience in analog circuit design, with a focus on I/O development and ESD/LU robustness.\nHands-on expertise with FinFet, FDSOI, and BCD process technologies from leading foundries.\nStrong background in ESD and Latch-Up qualification methodologies, including testchip development and validation.\nProficiency in ESD simulation, ESD network construction, and use of industry-standard tools.\nComprehensive understanding of PERC rules and practical experience with PERC verification tools.\nExperience working with cross-functional teams including foundry, design, and layout groups.</p>\n<p>Who You Are:\nAn analytical thinker with excellent problem-solving skills and keen attention to detail.\nA collaborative team player who values diversity, inclusion, and open communication.\nA proactive learner who stays current with industry trends and emerging technologies.\nAn effective communicator, able to translate complex technical information to diverse audiences.\nA results-driven individual who is adaptable, resilient, and comfortable with fast-paced, high-impact work.</p>\n<p>The Team You’ll Be A Part Of:\nYou’ll join a passionate, multidisciplinary team of analog and mixed-signal engineers dedicated to advancing Synopsys’ interface IP portfolio. The team is focused on delivering robust, innovative, and high-quality solutions that meet the rigorous demands of a global customer base. Collaboration, continuous improvement, and technical mentorship are at the core of our culture, ensuring you’ll have the support and opportunities needed to thrive and grow.</p>\n<p>Rewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2f942bce-976","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/analog-design-sr-engineer/44408/92446615456","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Analog circuit design","ESD and Latch-Up robustness","FinFet, FDSOI, and BCD process technologies","ESD simulation","PERC rules and verification tools","Cross-functional team collaboration"],"x-skills-preferred":["Machine learning","Artificial intelligence","Cloud computing"],"datePosted":"2026-03-08T22:19:02.488Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Analog circuit design, ESD and Latch-Up robustness, FinFet, FDSOI, and BCD process technologies, ESD simulation, PERC rules and verification tools, Cross-functional team collaboration, Machine learning, Artificial intelligence, Cloud computing"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c572da30-7d1"},"title":"Staff Analog & Mixed Signal Layout Engineer","description":"<p>We are seeking a highly skilled and collaborative engineer with a deep passion for analog and mixed-signal design. Your expertise spans advanced CMOS layout techniques, and you thrive in environments where technical complexity and innovation intersect. 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As a key member of our Customer Application Services team, you will provide expert support and training to customers on Totem and related Semiconductor Business Unit simulation products.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Provide expert support and training to customers on Totem and related Semiconductor Business Unit simulation products, ensuring high productivity and satisfaction.</li>\n<li>Independently coordinate and manage support for multiple customer designs through tape-out, verifying design quality and compliance with expectations.</li>\n<li>Apply advanced knowledge in analog circuit analysis, VLSI design, power-grid extraction, noise analysis, and ESD to solve complex SoC challenges.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering (BSEE/MSEE) with at least 3 years of relevant experience.</li>\n<li>Advanced expertise in custom circuit analysis &amp; design, physical layout, noise analysis, voltage drop effects, and ESD using CAD tools.</li>\n<li>Strong technical knowledge of EDA tools, especially for layout and analog circuit extraction (SPEF/DSPF).</li>\n<li>Proficiency in UNIX operating systems and scripting languages such as Perl, Tcl, or Python for troubleshooting and utility development.</li>\n<li>Excellent verbal and written communication skills in both English and Mandarin, with the ability to convey complex concepts clearly.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a010ce93-7a9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/zhubei/applications-engineering-sr-engineer-totem/44408/90398128240","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["custom circuit analysis & design","physical layout","noise analysis","voltage drop effects","ESD"],"x-skills-preferred":["UNIX operating systems","scripting languages","EDA tools"],"datePosted":"2026-03-06T07:33:28.198Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Zhubei, Taiwan"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"custom circuit analysis & design, physical layout, noise analysis, voltage drop effects, ESD, UNIX operating systems, scripting languages, EDA tools"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5a1f10d9-1d4"},"title":"Analog Layout Design, Staff Engineer","description":"<p>We are seeking an experienced Analog Layout Staff Engineer to join our team in Hanoi. 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