Your primary focus will be on validating the performance of autonomy and flight control software, ensuring that our systems meet the required standards. You will write test analyzers in Python to report and benchmark performance and qualification metrics of the system, produce test coverage and release-readiness reports, and recommend improvements to our simulation models and fault injection.

To succeed in this role, you will need 5+ years of work experience in testing complex integrated software systems, demonstrated expertise in test automation, and strong experience with the software product development lifecycle. A B.S., M.S, or PhD degree in Systems Engineering, Software Engineering, Computer Science, or a related field is also required.

In addition to a competitive salary ranging from $110,000 to $170,000 per year, you will receive a bonus, benefits, and equity as part of our full-time regular employee offer package.

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This role sits at the intersection of networking, distributed systems, and autonomy infrastructure, and is critical to our ability to deploy robust autonomous systems in real-world operations.

Key responsibilities include:

• Leading the development of the EdgeOS Communication stack used in deployed systems.
• Owning the architecture, implementation, and integration of high-performance C++ networking components.
• Developing and optimizing transport- and application-layer networking features for reliable, low-latency communication.
• Collaborating closely with autonomy, systems, and simulation teams.
• Supporting development of network simulation capabilities used for testing and validation in simulated environments.

Required qualifications include:

• A Bachelor's degree in Computer Science, Electrical Engineering, or a related field.
• At least 10 years of related experience with a Bachelor's degree; or 7 years and a Master's degree; or 5 years with a PhD; or equivalent work experience.
• Proficiency with C++ 11 or newer in a production environment.
• Understanding of networking fundamentals across IP, TCP/UDP, routing, QoS, and hands-on experience with network debugging and analysis tools.
• Experience developing and debugging distributed or networked systems.
• A proven track record of leading and delivering complex technical projects with minimal oversight.

Preferred qualifications include:

• Experience with C++17 or newer standards.
• Knowledge of CMake and Conan build systems.
• Background in distributed systems, simulation, or autonomous robotics environments.
• Experience with network emulation or simulation tools.
• Familiarity with RF communication systems or wireless networking concepts.

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This role is heavily weighted toward detection engineering. You should think in terms of adversary behaviour and telemetry coverage, not just alert triage. You'll own detections end-to-end: from identifying gaps in coverage, through designing and testing detection logic, to tuning and validating in production.

Key Responsibilities:

• Design, build, test, and tune high-fidelity detection rules and analytic queries across endpoint, cloud, network, identity, and DLP telemetry sources

• Develop and maintain detection content using detection-as-code practices including version-controlled logic, automated testing, and CI/CD deployment

• Map detection coverage to MITRE ATT&CK, identify gaps, and prioritise new detection development based on threat intelligence and business risk

• Engineer correlation rules, behavioural analytics, and anomaly-based detections that minimise false positives while surfacing real adversary tradecraft

• Own the detection lifecycle from initial development through production tuning, performance monitoring, and retirement

• Build and operate pipelines to ingest, normalise, enrich, and manage security telemetry at scale across diverse data sources, using Terraform and infrastructure-as-code practices to deploy and maintain logging and detection infrastructure

• Design and maintain log collection, parsing, and enrichment configurations that ensure the right telemetry is available at the right fidelity for detection and investigation

• Evaluate and onboard new telemetry sources as Saronic's infrastructure and threat landscape evolve

• Monitor pipeline health, data quality, and ingestion reliability to ensure detections operate on complete and accurate data

• Develop and manage automated response playbooks in SOAR platforms to accelerate containment and reduce analyst toil

• Build automation that enriches alerts with contextual data, reducing investigation time and improving analyst decision-making

• Support incident response efforts and translate lessons learned into improved detections and playbooks

• Partner with SOC analysts, Cloud Security, Product Security, and IT teams to close visibility and detection gaps across environments

• Collaborate with threat intelligence to ensure detection engineering is informed by current adversary TTPs relevant to defence, maritime, and autonomous systems

Required Qualifications:

• 3+ years of hands-on experience in detection engineering, security operations, security automation, or a closely related security engineering role

• Demonstrated experience designing, testing, and tuning detection rules and analytic queries across production security telemetry (endpoint, cloud, network, identity, or DLP)

• Hands-on experience with SIEM platforms and proficiency with query languages such as SPL, KQL, or equivalent

• Experience building and operating security data pipelines, including log ingestion, normalisation, enrichment, and data quality management

• Understanding of data engineering concepts including ETL pipelines, data modelling, schema design, and indexing as applied to security telemetry

• Hands-on coding experience in Python, PowerShell, Go, or Rust for security automation, detection tooling, or pipeline development, and familiarity with Terraform for managing detection and logging infrastructure as code

• Understanding of MITRE ATT&CK framework and its application to detection coverage and gap analysis

• Ability to obtain and maintain a security clearance

Preferred Qualifications:

• Experience in defence, aerospace, robotics, autonomy, or other high-assurance environments

• Experience with EDR platforms including custom detection rule creation and telemetry analysis

• Experience with cloud-native detection in AWS and Microsoft 365/Azure

• Experience using Terraform to deploy and manage security monitoring infrastructure, log pipeline components, or cloud-native security service configurations

• Hands-on experience with incident response, threat hunting, or adversary emulation

• Exposure to embedded Linux, operational technology, or ICS telemetry and detection

• Familiarity with NIST SP 800-171, NIST SP 800-53, or CMMC and their logging and monitoring requirements

• Relevant certifications such as GCIH, GCIA, GCDA, GSOM, OSDA, or OSCP

Additional Information:

• Benefits: Medical Insurance, Dental and Vision Insurance, Time Off, Parental Leave, Competitive Salary, Retirement Plan, Stock Options, Life and Disability Insurance, Pet Insurance

• This role requires access to export-controlled information or items that require 'U.S. Person' status.

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Director of Product Management

Sunnyvale, California, United States

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Category: Product ManagementHire Type: Employee

Job ID 15974Base Salary Range $200000-$300000Date posted 03/16/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a strategic, technically savvy leader who thrives at the intersection of product, marketing, and sales. With a deep-rooted engineering foundation and a passion for semiconductor and EDA solutions, you know how to convert complex technical capabilities into compelling market narratives. You are energized by the challenge of modernizing outbound marketing, leveraging AI-driven workflows, and building scalable systems that enable teams to deliver consistent, high-impact messaging and campaigns. Your experience spans hands-on engineering roles, technical product marketing, and sales enablement, making you a credible partner for both technical and business stakeholders.

You understand the nuances of hardware-assisted verification, emulation, and prototyping, and can translate intricate workflows into clear, customer-relevant value propositions. You possess the ability to engage deeply with engineering and field teams, bridging technical detail with executive-level messaging. You have a track record of mentoring marketing talent, driving cross-functional alignment, and elevating the quality and effectiveness of outbound efforts. You are comfortable working in a hybrid environment, collaborating with diverse teams, and leading through influence. Your commitment to continuous improvement and adoption of AI tools positions you as a role model for modern marketing excellence. Above all, you are motivated by the opportunity to scale impact, drive clarity, and help Synopsys’ most advanced solutions shine in the market.

What You’ll Be Doing:

• Design and execute end-to-end outbound marketing campaigns for key semiconductor and EDA solution areas, including product launches and major industry events.

• Craft clear messaging frameworks, value propositions, and narratives that translate technical differentiation and customer use cases into market-ready content.

• Develop and maintain practical sales enablement playbooks,including buyer personas, competitive positioning, objection handling, pitch decks, demo guidance, and talk tracks.

• Lead outbound positioning and enablement for hardware-assisted emulation, FPGA-based prototyping, hybrid verification flows, and software enablement solutions.

• Apply AI tools and workflows to accelerate content creation, synthesize market feedback, and establish scalable, repeatable marketing best practices.

• Collaborate closely with Product Management, Product Marketing, Sales, Field Engineering, PR, and Events to ensure consistent, credible, and high-impact market engagement.

• Mentor and elevate marketing talent, introducing frameworks, standards, and best practices to modernize execution and foster cross-functional alignment.

The Impact You Will Have:

• Transform bespoke outbound efforts into scalable, repeatable systems that amplify market reach and sales effectiveness.

• Increase clarity and credibility for Synopsys’ most advanced technical solutions, ensuring consistent messaging across channels.

• Empower sales teams with practical, field-ready enablement assets that resonate with highly technical buyers and senior executives.

• Drive adoption of AI-first marketing workflows, setting new standards for speed, quality, and insight generation.

• Bridge the gap between engineering teams and market-facing functions, ensuring alignment and real-world relevance in all outbound content.

• Elevate the quality and impact of outbound marketing programs tied to industry moments, launches, and customer engagements.

• Mentor and develop marketing talent, fostering a culture of excellence, innovation, and cross-functional collaboration.

What You’ll Need:

• 10+ years of experience in product marketing, outbound marketing, sales enablement, or technical marketing within semiconductors or EDA.

• Strong engineering foundation,experience as a design, verification, systems, applications, or field engineer, or as a technically deep product marketer.

• Demonstrated understanding of hardware-assisted verification, including emulation and prototyping workflows and use cases.

• Proven ability to translate complex technical concepts into compelling outbound messaging and sales enablement assets.

• Hands-on expertise with AI tools to enhance marketing productivity, content creation, and insight generation.

• Strong written and verbal communication skills, with the ability to influence both technical and non-technical audiences.

• Experience supporting high-value B2B technical sales cycles and product launches tied to major industry events.

Who You Are:

• Strategic thinker with a growth mindset and a passion for continuous improvement.

• Collaborative leader who thrives in cross-functional environments and leads through influence rather than authority.

• Technically credible and able to engage deeply with engineering, product, and field teams.

• Adaptable and comfortable navigating fast-paced, complex environments with evolving priorities.

• Empathetic mentor and coach, committed to elevating team capabilities and setting new standards for marketing excellence.

• Detail-oriented, yet able to distill complexity into clear, actionable messaging for diverse audiences.

• Innovator who embraces AI-driven workflows and modern marketing practices.

The Team You’ll Be A Part Of:

You will join a dynamic and collaborative Product Management and Product Marketing leadership team, working closely with Sales, Field Engineering, PR, and Events. This group is focused on scaling outbound marketing execution, driving clarity and credibility for Synopsys’ most advanced solutions, and embracing AI-first ways of working. Together, you will foster cross-functional alignment, elevate marketing talent, and deliver high-impact programs that shape the industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Senior Engineer in the R&D department, you will be responsible for developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI. You will implement designs in C++, RTL, and SystemVerilog-DPIs, and collaborate with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments. You will also create and optimize use models and applications for various emulation projects, conduct thorough verification and validation processes to ensure the highest quality of emulation models, and provide technical guidance and mentorship to junior team members when necessary.

Key responsibilities include:

• Developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI.
• Implementing designs in C++, RTL, and SystemVerilog-DPIs.
• Collaborating with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments.
• Creating and optimizing use models and applications for various emulation projects.
• Conducting thorough verification and validation processes to ensure the highest quality of emulation models.
• Providing technical guidance and mentorship to junior team members when necessary.

As a member of the Emulation Transactor Development Team, you will work closely with various teams across the organization to ensure the highest quality in our products. Our collaborative and inclusive environment encourages innovation, continuous learning, and personal growth.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We currently have 614 open roles

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a technically accomplished and strategically minded architect who thrives at the intersection of technology and business. You bring a deep passion for power and performance analysis technologies and system-level validation, and are adept at translating complex technical concepts into actionable product strategies and compelling business opportunities.

Drive the full lifecycle of power and performance analysis solutions,from ideation and design through development, launch, and market adoption.

Develop and execute long-term product and technology roadmaps that align with customer needs and corporate strategy.

Serve as the domain and product expert for power and performance analysis solutions, with a focus on use-case-driven development.

Develop Product Requirements Documents (PRDs) based on customer use cases and translate them into detailed feature definitions in collaboration with Product Engineering (PE) and Product Management (PM) teams.

Guide product management on release content, prioritization, and readiness reviews in coordination with R&D and PE teams.

Define and co-create Application Engineering (AE) training materials for use case enablement.

Conduct technical win/loss analyses and competitive benchmarking to inform product positioning and roadmap decisions.

Create technical collateral including blogs, whitepapers, demos, and presentations to support go-to-market efforts.

Engage with customers and field teams to gather feedback, validate product direction, and ensure alignment with market needs.

Lead strategic initiatives and cross-functional projects that deliver measurable business impact.

Shape the strategic direction and long-term success of Synopsys’ Power and Performance Analysis Solutions portfolio.

Drive customer-centric innovation that positions Synopsys as a market leader in power modeling and validation technologies.

Influence industry standards and market trends through active participation in technical forums and standards bodies.

Accelerate revenue growth by identifying new market opportunities and developing effective go-to-market strategies.

Enhance cross-functional collaboration, ensuring seamless product execution and high customer satisfaction.

Foster a culture of innovation, learning, and continuous improvement within the organization.

Build strategic partnerships and new market entry models to differentiate Synopsys’ offerings.

Anticipate and address future market needs, ensuring ongoing competitiveness and relevance.

Deep technical expertise in power & performance modeling, emulation platforms, RTL simulation, and power-aware design flows.

5+ years of experience in technical product management, preferably in EDA, semiconductor, or system design domains.

Proven ability to define and execute product strategies based on technical use cases and market trends.

Strong analytical skills, with experience in market analysis, business planning, and competitive assessment.

Excellent verbal and written communication skills, including the ability to present and influence at all organizational levels.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field (MBA preferred).

A collaborative and inclusive leader who inspires trust and drives results through cross-functional teamwork.

Strategic thinker with the ability to anticipate future trends and proactively shape product direction.

Customer-focused, with a passion for understanding and solving complex customer challenges.

Excellent communicator, adept at tailoring messages to diverse audiences and building strong relationships.

Resilient, adaptable, and comfortable navigating ambiguity in a fast-paced, dynamic environment.

Committed to fostering a culture of learning, innovation, and continuous improvement.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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This role is for a Pre-Silicon Signoff Lead who will be responsible for leading simulation and sign-off activities that guarantee reliability and performance. The ideal candidate will have a rich background in high-speed serial communication and advanced transceiver design, with expertise in theoretical modeling and hands-on lab work.

Key responsibilities include collaborating closely with analog, digital, and hardware teams to ensure comprehensive design and verification coverage, developing and maintaining robust simulation and verification plans for IP, and reviewing progress against verification plans through regular meetings with multiple verification teams.

The successful candidate will have a strong command of simulation, verification, and hardware validation processes, with experience in high-speed protocols such as PCIe and Ethernet. They will also have a proven track record of leadership in testbench architecture, planning, cross-site collaboration, and mentoring.

As a member of our world-class engineering team, you will drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications.

If you are an innovative and forward-thinking engineer with a passion for advancing connectivity technologies, we encourage you to apply for this exciting opportunity.

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As a Sr. Staff Engineer, you will be a key member of our Emulation/Validation team, responsible for bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.

Key responsibilities include:

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.
• Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.
• Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement.

The impact you will have includes enhancing cross-functional collaboration to elevate product quality and end-customer satisfaction, transforming the approach to Emulation IP usage in validating cutting-edge digital designs and system architectures, and driving innovation by defining and refining requirements for IP product development, particularly in emulation contexts.

To succeed in this role, you will need 8+ years of relevant experience in emulation, verification, or IP product development, expert-level knowledge of PCIe/ DDR/ Ethernet interfaces, including protocol and verification strategies, extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification, and a demonstrated track record in leading IP product development initiatives with a focus on emulation.

If you are a proactive and collaborative problem-solver with a passion for excellence, innovative thinker who embraces change and seeks out opportunities for continuous improvement, strong communicator able to articulate complex technical concepts to diverse audiences, resilient and adaptable, thriving in dynamic environments and embracing new challenges, and committed to mentoring others and fostering an inclusive, team-oriented culture, then we encourage you to apply for this exciting opportunity.

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Designing, developing, and maintaining Speed Adapter solutions for advanced protocols, including PCIe and CXL. Implementing protocol functionality on FPGA-based platforms to bridge real-world I/O with DUTs running at reduced speeds on emulation and prototyping systems. Collaborating with IP, emulation, and prototyping teams to deliver comprehensive, end-to-end system-level validation solutions. Developing and debugging RTL, firmware, and system-level components for Speed Adapter products. Supporting seamless integration with ZeBu and HAPS platforms, including creating example designs and reference flows. Participating in customer escalations, conducting root-cause analysis, and delivering solutions for complex system-level issues. Contributing to roadmap planning, feature definition, and technical differentiation versus competitive solutions.

Enable customers to connect pre-silicon designs to real devices, testers, and hosts with unmatched fidelity and performance. Advance industry-leading system-level validation technology for top semiconductor and hyperscale customers. Shape the adoption and implementation of next-generation protocols such as PCIe Gen6/Gen7 and CXL3.x/4.0. Drive innovation in hardware-assisted verification, influencing patent-pending technologies that differentiate Synopsys solutions. Enhance integration across IP, emulation, prototyping, and real-world connectivity to deliver robust validation platforms. Support global teams and customers, fostering technical excellence and collaborative problem-solving.

12 years+ relevant experience Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. Strong hands-on experience with PCIe and/or CXL protocols, including implementation and debugging. Solid understanding of digital design, RTL development, and FPGA-based systems. Experience with system-level validation, emulation, or prototyping environments. Familiarity with high-speed serial interfaces and real-world I/O connectivity. Strong debugging skills across RTL, firmware, and hardware/software boundaries. Ability to work effectively in a cross-geography, cross-functional team.

Innovative thinker with a strategic mindset. Collaborative team player who values diverse perspectives. Excellent communicator and technical mentor. Resilient problem-solver, able to navigate ambiguity and complexity. Customer-focused, with a commitment to delivering high-impact solutions. Adaptable and proactive, eager to stay ahead in a fast-evolving technology landscape.

You'll join the Speed Adapter engineering team within Synopsys' HW-Assisted Verification (HAV) organization. This talented group is dedicated to developing and deploying industry-leading Speed Adapter solutions that bridge advanced protocols and real-world interfaces with ZeBu emulation and HAPS prototyping platforms. The team collaborates globally across IP, emulation, and prototyping domains to deliver robust, high-performance system validation solutions, directly impacting the success of top semiconductor and hyperscale customers.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

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Job Summary

You are a passionate and driven professional with a profound mastery of hardware-assisted verification (HAV), using emulation and FPGA prototyping methodologies, with a sharp focus on performance optimization. Your expertise covers the entire lifecycle of HW/SW product development, from early RTL verification to software bring up and platform delivery.

Responsibilities

• Drive advanced product capabilities and innovations in emulation runtime performance for industry-leading platforms.
• Engage in the full product lifecycle, from feature definition and implementation to rigorous testing, quality measurement, and customer deployment.
• Collaborate closely with internal stakeholders, including Application Engineering peers and R&D teams, to deliver superior outcomes for customers.
• Provide technical leadership and product evaluation support to key emulation customers across the globe.
• Lead comprehensive root cause analyses to resolve and prevent emulation performance bottlenecks.
• Ensure the highest standards of verification for SoC designs, contributing to the creation of robust and reliable products.

What You’ll Need

• Minimum 12+ years of experience in emulation methodology, spanning early RTL verification to software bring up.
• Proven expertise in verification, with a focus on System on Chip (SoC) design bring-up and validation.
• Comprehensive knowledge of the architecture of emulation / FPGA prototyping platforms and their eco-systems.
• A good understanding of the compilation and runtime flows on these emulation platforms.
• Demonstrated experience in using debug features of these emulation platforms, and in conducting root cause analysis for emulation runtime performance issues.

Benefits

• Competitive salary and benefits package
• Opportunities for career growth and professional development
• Collaborative and dynamic work environment
• Recognition and rewards for outstanding performance

Who You Are

• A collaborative team player who thrives in dynamic, fast-paced environments.
• Detail-oriented and analytical, with exceptional problem-solving skills.
• Curious, adaptable, and eager to embrace new challenges and responsibilities.
• An effective communicator, skilled at conveying complex technical information to diverse audiences.
• An innovative thinker with a passion for continuous improvement and learning.

The Team You’ll Be A Part Of

You’ll join the Product Engineering (PE) team within the TPG division at Synopsys Bangalore office. This team is at the forefront of delivering and deploying next-generation performance technologies in ZeBu platforms to customers worldwide. As a pivotal member, you will engage in technically challenging projects with significant responsibilities and visibility, all while enjoying a supportive environment that fosters career growth, innovation, and professional development.

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Responsibilities:

• Collaborate with R&D architects and customers on hardware-assisted verification products.

• Drive all aspects of the technology life cycle, from development to product sign-off and customer deployment.

• Define test strategies and methodologies to improve ease-of-use, quality of results, and interoperability with other Synopsys tools.

• Become an expert in emulation and prototyping methodologies and flows, including design, partitioning, testing, synthesis, and simulation-based verification.

• Leverage your close interaction with customers, R&D, Marketing, and Sales teams to demonstrate the differentiated emulation/verification environment.

• Adapt to recognised best practices and policies in Synopsys to become proficient in various processes involved in the Product Release Cycle.

• Work with designs from varied verticals to enable and support key ZeBu products in early-stage development.

The Impact You Will Have:

• Enhance Synopsys' emulation and prototyping solutions by driving technology development and customer deployment.

• Improve the ease-of-use, quality of results, and interoperability of Synopsys tools, contributing to overall product excellence.

• Provide expert consultation for solving complex problems, thereby increasing customer satisfaction and product adoption.

• Ensure successful execution of projects from start to completion, contributing to the timely delivery of high-quality products.

• Support the advancement of cutting-edge designs in various verticals such as HPC, AI, storage, networking, and automotive.

• Facilitate the proliferation of Synopsys' differentiated emulation/verification environment through close collaboration with multiple teams.

What You’ll Need:

• BSEE/MS with 7+ years of related experience.

• Expertise in Emulation and/or Prototyping flows, systems, and methodologies.

• Strong proficiency in Verilog, System Verilog, and VHDL.

• Understanding of verification concepts and experience with functional simulators.

• Experience with scripting languages.

• Knowledge in Simulation flows, Assertion, DPI, and Transactors.

• Complex problem-solving and debugging skills.

• Strong communication skills and the ability to interact with customers and peers.

• Knowledge in synthesis and timing analysis concepts (preferred).

• Familiarity with Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality (preferred).

• Experience with Xilinx & Altera architecture and toolchains (preferred).

• Understanding of SW/HW debug methodologies and experience with standard SW/HW debug tools (preferred).

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key responsibilities include:

• Defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability.
• Driving the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.
• Mapping RTL designs into FPGA environments, utilizing deep verification and implementation knowledge to facilitate smooth prototyping and validation.
• Generating and packaging diagnostic tests for both production and field use, ensuring robust system performance and rapid troubleshooting.

As a Staff Hardware Engineer, you will work closely with cross-functional teams to accelerate the development of next-generation technologies through advanced FPGA design and integration. You will strengthen team productivity and knowledge by actively collaborating, mentoring, and sharing expertise with colleagues.

Requirements include:

• BS/MS in Computer Science, Electrical Engineering, or a related field.
• 5+ years of hands-on experience in RTL design and verification, preferably with complex FPGA systems.
• Proficiency in Hardware Description Languages such as VERILOG, VHDL, or SystemVerilog.
• Expertise in using industry-standard EDA tools and methodologies for design and verification.
• Hands-on experience with FPGA flows and tools like Vivado, and familiarity with Unix/Linux environments.
• Experience with scripting languages (Shell, Perl, Python, TCL) for automation and productivity enhancement.
• Background in HDL simulation, emulation, and prototyping platforms (e.g., Zebu, HAPS).
• Strong logical thinking and problem-solving abilities, with a keen attention to detail.

Benefits include:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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You are an accomplished engineering leader with more than a decade of hands-on experience in SoC verification, emulation, and system-level validation. You thrive at the intersection of advanced hardware-assisted verification (HAV) and simulation acceleration (SimXL), bringing a deep understanding of complex SoC architectures, memory subsystems, and high-speed interconnects.

Architecting and leading Hardware-Assisted Verification and Simulation Acceleration solutions for large-scale SoCs and multi-die systems.

Driving end-to-end SimXL deployments, including use-case definition, performance optimization, and methodology standardization.

Defining and owning system-level verification and acceleration strategies spanning simulation, emulation, and prototyping.

Bridging gaps between RTL simulation, emulation, and software bring-up to enable early and scalable system validation.

Leading complex customer engagements involving HAV platforms, simulation acceleration, and hybrid verification flows.

Translating customer verification challenges into scalable, reusable solution architectures and acting as a technical authority in escalations.

Driving innovation in HAV and SimXL methodologies, including automation, reuse, and productivity frameworks leveraging AI/GenAI-assisted approaches.

Collaborating with R&D, Product Management, and Applications teams to influence product roadmaps and feature requirements.

Accelerate customer verification cycles, enabling earlier software and system bring-up for complex SoC designs.

Define and scale best-in-class HAV and SimXL solutions across strategic accounts, enhancing customer outcomes.

Drive measurable improvements in performance, capacity, and debug productivity for verification workflows.

Shape the future of AI-assisted verification and solution deployment within Synopsys and across the industry.

Act as a key technical leader in advancing the organization’s verification acceleration strategy.

Mentor and empower senior engineers, fostering a culture of innovation and technical excellence.

Influence product direction and solution roadmaps through deep technical insights and customer engagement.

10+ years of experience in SoC verification, emulation, or system-level validation.

Deep hands-on expertise in Hardware-Assisted Verification, simulation acceleration, and hybrid verification flows.

Strong experience with emulation platforms and accelerated simulation environments.

Solid understanding of SoC architectures, interconnects, memory subsystems, and software bring-up challenges.

Proven ability to design and deploy scalable verification solutions for complex designs.

Experience with system-level testbenches, transactors, and acceleration frameworks.

Exposure to GenAI or AI-assisted techniques applied to verification, debug, or solution automation.

Background in high-speed interfaces, memory subsystems, or multi-die architectures.

Track record of creating reusable assets, methodologies, or automation frameworks.

Experience influencing product direction or defining solution roadmaps.

Innovative thinker with a passion for driving technological advancement and automation.

Collaborative leader who mentors and inspires teams across geographies.

Strong communicator adept at translating complex technical concepts for diverse audiences.

Customer-focused problem solver with a commitment to delivering impactful solutions.

Adaptable and resilient in fast-paced, matrixed environments.

Detail-oriented, analytical, and proactive in identifying and addressing challenges.

You will join a dynamic, cross-functional team dedicated to advancing verification acceleration solutions for Synopsys’ strategic customers. The team comprises experts in HAV, simulation acceleration, R&D, product management, and applications engineering, all working collaboratively to define and deploy innovative methodologies.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You will report key metrics and drive continuous improvement initiatives in Emulation IP quality and performance.

You will provide technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.

You will stay ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.

You will review and validate test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.

You will collaborate cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.

You will mentor and guide junior engineers, fostering a culture of innovation and continuous improvement.

This role requires 10-20 years of relevant experience in emulation, verification, or IP product development.

You should have expert-level knowledge of PCIe and DDR interfaces, including protocol and verification strategies.

You should have extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

You should have demonstrated track record in leading IP product development initiatives with a focus on emulation.

You should have strong background in cross-functional collaboration, with an ability to drive consensus and deliver results.

You should have outstanding communication skills, with the ability to influence and inspire change across diverse teams.

You should be adaptable and comfortable working in a fast-paced, matrixed, and international environment.

As a proactive and collaborative problem-solver with a passion for excellence, you will be a strong fit for this role.

You will join a dynamic, high-performing engineering team focused on IP development, emulation, and verification at the forefront of semiconductor innovation.

Our team is collaborative, cross-functional, and globally distributed, working together to solve complex challenges and deliver industry-leading solutions.

You will have the opportunity to collaborate with experts across multiple domains, drive impactful initiatives, and shape the future of digital design and verification at Synopsys.

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They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

Responsibilities

• Design, implement, and optimize compilation algorithms for mapping large-scale processor hardware descriptions onto the ZeBu emulator
• Develop scalable solutions to handle multi-billion-gate designs within tight runtime and memory constraints
• Apply advanced problem-solving skills to debug complex compilation, placement, and performance issues
• Develop and maintain high-quality, modular, and extensible object-oriented software in C++
• Collaborate closely with hardware architects, performance engineers, and emulator platform teams to ensure seamless integration and performance
• Contribute to continuous improvement of compilation flows, algorithms, and infrastructure for enhanced efficiency and robustness
• Participate in code reviews, design discussions, and knowledge sharing sessions with the broader engineering community

Impact

• Enable leading semiconductor companies to verify next-generation processor designs before commercialization
• Drive performance and scalability improvements, reducing compile and placement times for massive hardware designs
• Advance state-of-the-art compilation technologies in emulation, directly shaping the future of chip verification
• Enhance robustness and reliability of the ZeBu emulation platform, ensuring successful deployment in real-world scenarios
• Foster innovation and collaboration within the ZeBu Compiler Team and across Synopsys engineering groups
• Support industry leaders in achieving faster time-to-market for their products through efficient emulation workflows
• Champion best practices in software engineering, contributing to the overall quality and maintainability of the codebase

Requirements

• 3-5 years of relevant experience
• Strong skills in problem solving and algorithmic thinking, with proven experience in tackling challenging technical problems
• Solid expertise in object-oriented programming (preferably C++)
• Deep understanding of data structures and algorithms, with the ability to design efficient and scalable solutions
• Experience working with complex systems and large codebases
• Strong analytical skills and meticulous attention to detail
• Exposure to performance optimization, memory efficiency, or parallel computing (preferred)
• Familiarity with hardware description languages (Verilog, SystemVerilog, VHDL) (preferred)
• Experience with emulation, FPGA, EDA tools, or large-scale system software (preferred)

Team

You’ll join the ZeBu Compiler Team,a group of passionate engineers dedicated to advancing emulation technology for the world’s leading semiconductor companies. The team focuses on developing innovative compilation algorithms, scalable software solutions, and robust infrastructure to enable efficient verification of massive hardware designs. Collaboration, knowledge sharing, and a commitment to excellence define the team’s culture, empowering each member to make a meaningful impact.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk.

You Are:

You are a talented Firmware Development Engineer with a passion for embedded systems and software innovation. You thrive in environments where high-speed and precision matter, bringing a strong programming background and an aptitude for developing reliable, scalable firmware solutions. Your expertise in C programming and familiarity with scripting languages such as Perl, TCL, or Python make you a versatile contributor. You are experienced in developing firmware for complex embedded systems and high-speed interfaces, and you take pride in rigorous problem-solving and debugging. You enjoy collaborating with hardware engineers to ensure seamless integration between firmware and hardware, and you are skilled at navigating verification and emulation environments to enhance product quality. Your attention to detail and commitment to delivering robust, high-quality firmware are matched by your ability to adapt to new challenges in a fast-moving industry. You value diversity and inclusion, and you are comfortable working in a dynamic, multicultural team. Whether you are mentoring junior engineers, spearheading integration efforts, or contributing to pre-silicon environments, you consistently demonstrate initiative, innovation, and a collaborative spirit. If you are excited to power the Era of Smart Everything and help shape tomorrow’s breakthroughs, you’ll find your place at Synopsys.

What You’ll Be Doing:

• Designing and implementing firmware for high-speed PHY IPs using C programming.
• Developing and maintaining software development environments and tools to streamline workflows.
• Collaborating with hardware engineers to ensure firmware compatibility and optimized integration with hardware designs.
• Conducting rigorous unit testing and debugging to ensure high-quality firmware performance
• Utilizing verification and emulation environments to enhance the integration process and support pre-silicon development.
• Documenting design processes, maintaining code quality, and ensuring compliance with industry standards.
• Staying current with emerging technologies in embedded systems and high-speed interfaces.

The Impact You Will Have:

• Accelerating the integration of advanced capabilities into SoCs through robust firmware development.
• Enhancing product reliability, performance, and time-to-market for customers in diverse industries.
• Supporting the development of differentiated products that power innovations like AI, 5G, IoT, and self-driving cars.
• Reducing risk and optimizing project outcomes by leveraging your expertise in embedded systems and high-speed interfaces.
• Driving cross-functional collaboration between software and hardware teams to deliver seamless solutions.
• Contributing to Synopsys’ leadership in silicon IP and embedded technology by delivering high-quality, scalable firmware.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Strong programming skills in C and familiarity with software development methodologies.
• Experience with scripting languages such as Perl, TCL, or Python.
• Proven experience in firmware development for complex embedded systems or high-speed interfaces.
• Excellent problem-solving and debugging skills, especially in unit testing and integration scenarios.
• Knowledge of high-speed interface protocols such as DDR, LPDDR (preferred).
• Experience with pre-silicon environments, including verification or emulation (preferred).

Who You Are:

• Analytical, detail-oriented, and committed to delivering high-quality results.
• Collaborative and effective communicator, able to work across diverse teams and disciplines.
• Adaptable and eager to learn new technologies and methodologies.
• Proactive, with a passion for innovation and continuous improvement.
• Inclusive and respectful, supporting a diverse and multicultural work environment.

The Team You’ll Be A Part Of:

You will join a vibrant Silicon IP engineering team dedicated to developing and integrating advanced firmware for high-speed interfaces. The team consists of experts in embedded systems, software, and hardware design, working together to solve complex challenges and deliver industry-leading solutions. Collaboration, innovation, and a commitment to excellence define the team’s culture as they support customers in bringing differentiated products to market quickly and efficiently.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Design Verification Engineer

Location

San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Scaling

Compensation

• $226K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team:

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.

In this role you will:

• Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.

• Define verification plans based on architecture and microarchitecture specs.

• Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.

• Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.

• Drive bug triage, root cause analysis, and work closely with design teams on resolution.

• Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.

You might thrive in this role if you have:

• BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.

• Proven success verifying complex IP or SoC designs in industry-standard flows

• Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).

• Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.

• Familiarity with performance modeling, formal verification, or emulation is a plus.

• Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $123K – $285K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We are seeking an experienced ASIC Strategic Sourcing and EDA/IP Licensing Strategy Partner Manager to lead strategy, sourcing, and vendor partnerships across OpenAI’s chip, system, and emulation ecosystem. This is a highly cross-functional role, driving supplier selection, contract negotiations, and ongoing vendor management for the tools, IP, and systems that underpin OpenAI’s most ambitious hardware programs.

As OpenAI scales silicon, system design, and cross-org research needs, you will be the single-threaded owner for EDA/IP, emulation, and chip supplier engagements. Your work will directly accelerate program execution velocity, secure mission-critical capacity, and strengthen executive-level vendor relationships. You will have an opportunity to drive vendor optimization by providing clarity on needs, reducing duplicate licenses and unnecessary costs, accelerate contract execution to secure critical capacity on time, and build trusted partnerships with key suppliers. You will also help establish clear governance and scalable engagement frameworks that provide visibility into spend, utilization, and risk as OpenAI continues to grow.

Responsibilities

• Drive commercial structures and contracts ASICs including IP blocks, design services, verification, foundry/OSAT engagements, and NPI ramp support—ensuring shortened contract cycles and timely resource and capacity commitments.

• Lead end-to-end supplier and licensing strategy for EDA, IP, and large rack systems supporting OpenAI’s ASIC and infrastructure programs. Rationalize licensing across organizations to maximize efficiency and eliminate duplicate spend, influencing engineering to support strategic consolidation efforts.

• Own supplier/partner selection, evaluation, pricing, contracting, renewals, and performance management across current and future partners.

• Lead emulator negotiations, capacity planning, and usage agreements; develop escalation paths to meet critical engineering needs.

• Build durable executive relationships with suppliers/partners, run QBRs/TRMs, negotiate early-access programs, and align on joint roadmaps to provide visibility into OpenAI’s evolving supplier needs. Translate engineering requirements into sourcing specifications, terms, and license structures; manage vendor escalations and hold suppliers accountable for commitments.

• Partner closely with engineering, legal, and finance to balance trade-offs, serve as the single point of contact for Research/Scaling and other orgs, and ensure engagements are strategic rather than transactional to maximize OpenAI’s long-term leverage.

• Provide clear dashboards and reporting on spend, utilization, capacity, and risk.

Qualifications

• 8+ years in EDA/IP licensing/strategic sourcing, and supplier base strategy roles.

• Experience in ASIC partnerships/strategic sourcing and deep familiarity with vendors in supply chains and ecosystems

• Deep familiarity with vendors in EDA, IP, design services, and emulation.

• Strong commercial negotiation skills with a proven track record of securing favorable terms and managing complex contracts.

• Ability to partner with engineering leaders to translate technical needs into commercial outcomes.

• Executive maturity and presence to represent OpenAI’s interests in high-stakes negotiations and executive-level meetings.

• Strong analytical and problem-solving skills, with the ability to analyze complex data sets and develop insights that inform business decisions.

• Excellent communication and interpersonal skills, with the ability to effectively communicate with cross-functional teams, including engineering, sales, and executive stakeholders.

• Ability to work in a fast-paced environment and adapt to changing priorities and deadlines.

• Strong attention to detail and organizational skills, with the ability to manage multiple projects and priorities simultaneously.

• Bachelor’s degree in a related field (e.g. business, engineering, computer science).

• MBA or advanced degree preferred.

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What you'll do

• Drive advanced product capabilities and innovations in emulation runtime performance for industry-leading platforms.
• Engage in the full product lifecycle, from feature definition and implementation to rigorous testing, quality measurement, and customer deployment.
• Collaborate closely with internal stakeholders to deliver superior outcomes for customers.

What you need

• Minimum 8 years of experience in emulation methodology, spanning early RTL verification to software bring up.
• Proven expertise in verification, with a focus on System on Chip (SoC) design bring-up and validation.

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What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.

What you need

• 8+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe or DDR interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

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What you'll do

Develop advanced technologies to enhance hardware emulation performance and scalability.

• Developing advanced technologies to enhance hardware emulation performance and scalability.
• Analyzing and debugging complex problems that span hardware and software domains.
• Understanding and improving sophisticated emulation technologies, including clock processing and timing analysis.
• Proposing innovative ideas and solutions to optimize emulation workflows and system efficiency.
• Working across all aspects of the emulation flow, including compilation, runtime, and debug processes for next-generation products.

What you need

• Proficiency in C++ and demonstrated experience debugging complex systems.
• Hands-on experience with Verilog or VHDL and HDL simulation environments.
• Familiarity with Electronic Design Automation (EDA) and emulation technologies (desired).
• Strong analytical skills to tackle intricate hardware and software challenges with creative solutions.
• Solid understanding of verification flows, ASIC or FPGA workflows, and performance optimization strategies.
• Understanding of clocking challenges in ASIC and FPGA

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What you'll do

Collaborating closely with analog, digital, and hardware teams to ensure holistic design and verification coverage.

• Developing and maintaining comprehensive simulation and verification plans for IP, aligning with reliability and performance targets.

What you need

• MSc or PhD in Electrical/Computer Engineering, with 10+ years of relevant industry experience.

Why this matters

Advance high-speed connectivity for enterprise and hyperscale applications worldwide.

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What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.

What you need

• 8+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe/ DDR/ Ethernet interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

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What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.

What you need

• 15+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe/ DDR / Ethernet interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

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What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.

What you need

• 15+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe/ DDR / Ethernet interfaces, including protocol and verification strategies.

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What you'll do

Your hands-on approach and proactive attitude make you a go-to resource for bridging gaps between Emulation IP and Design IP, ensuring seamless integration and verification of both Controller and PHY components.

• Deliver robust, production-ready IP through rigorous emulation and verification cycles.

What you need

• A keen eye for detail and a commitment to right-first-time development, always ensuring traceability and completeness across verification requirements.

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What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.
• Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.
• Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement.

What you need

• 8+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe or DDR interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.
• Demonstrated track record in leading IP product development initiatives with a focus on emulation.
• Strong background in cross-functional collaboration, with an ability to drive consensus and deliver results.
• Outstanding communication skills, with the ability to influence and inspire change across diverse teams.
• Adaptability and comfort working in a fast-paced, matrixed, and international environment.

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