You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications.

Responsibilities

• Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.
• Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.
• Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.
• Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.
• Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.
• Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.
• Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

Impact

• Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets.
• Drive innovation in verification methodologies, setting new standards for efficiency and coverage.
• Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle.
• Strengthen Synopsys' reputation as a leader in silicon IP and verification through technical excellence and customer focus.
• Mentor and support junior engineers, fostering a culture of learning and continuous improvement.
• Contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.

Requirements

• BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.
• Expertise in developing HVL (System Verilog)-based verification environments and testbenches.
• Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.
• Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.
• Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.
• Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.
• Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.

Who You Are

• Analytical thinker with strong problem-solving and debugging skills.
• Excellent verbal and written communication abilities.
• Team player who thrives in collaborative, multi-site environments.
• Proactive, self-motivated, and able to take initiative on challenging projects.
• Detail-oriented, quality-focused, and driven by a desire to excel.
• Adaptable and eager to continuously learn and apply new technologies.

XML job scraping automation by YubHub

As an accomplished and forward-thinking ASIC Digital Design, Manager-IP Verification professional, you will lead and inspire a team dedicated to excellence in IP verification. Your expertise lies in architecting robust verification environments for complex serial protocols, leveraging HVL (System Verilog), and utilizing industry-standard simulators. You have a deep understanding of verification methodologies like VMM, OVM, and UVM, and are experienced with protocols such as MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB.

Your responsibilities will include specifying, designing, and implementing advanced verification environments for the DesignWare family of synthesizable cores, overseeing verification tasks for IP cores, developing and executing detailed test cases, debugging issues, coding for functional coverage, and ensuring rigorous testing to meet quality goals.

You will also manage regression processes and ensure strict adherence to industry-leading verification methodologies, collaborate closely with RTL designers and a global team of verification engineers to drive seamless integration and innovation, and lead efforts on next-generation connectivity protocols tailored for commercial, enterprise, and automotive markets.

This role requires a Bachelor's degree in Electrical Engineering (BSEE) with 10+ years of relevant experience, or Master's degree (MSEE) with 8+ years. You should have demonstrated experience architecting verification environments for complex serial protocols, proficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI, expertise in verification methodologies including VMM, OVM, and UVM, and strong knowledge of protocols (MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB).

You should be detail-oriented and analytical, with exceptional problem-solving skills, proactive and initiative-driven, able to anticipate challenges and opportunities, excellent communicator, both written and verbal, across diverse and global teams, collaborative team player, fostering a positive and inclusive work environment, adaptable and resilient, capable of managing multiple tasks and shifting priorities effectively.

XML job scraping automation by YubHub

We are seeking a creative and talented engineer to fill a FPGA Validation role in Bengaluru, India. The environment presents stimulating, challenging, and rewarding work within an excellent work environment with positive career development opportunities.

The FPGA Design and Verification IP Prototyping team is responsible to build FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs and test them to verify their compliance with leading edge industry standards. We play a vital role on supporting Synopsys IP business by validating key features, and mitigating ASIC potential faults early on, in a prototype.

Responsibilities:

• Design, implement, and verify FPGA-based systems for a variety of applications
• Validate FPGA-based IP prototype 'Device Under Test' against real-world devices, Test Equipment and other hardware systems
• Create and maintain comprehensive technical documentation
• Elaborate and execute test plans and test routines
• Detect, troubleshoot, debug, and investigate potential ASIC issues up front
• Establish and maintain relationships with cross-functional teams, internal and external customers

Key Qualifications:

• Bachelor's or master's degree in electrical engineering
• 5+ years of experience in FPGA design and development
• Design and simulate integrated circuitry using Verilog, System Verilog
• Expertise with industry-standard scripting languages such Tcl, Python, Perl and Bash
• Expertise with industry-standard interfaces and protocols such as AMBA AXI or APB.
• Experience with FPGA development tools such as XILINX Vivado. Familiarity with Synopsys Synplify or Protocompiler is a plus
• Experience in digital design methods such as floor planning, timing constraints definition, and static timing analysis
• Excellent verbal and written communication skills in English

Preferred Experience:

• Expertise with HAPS-100,HAPS-80 Boards and Protocompiler Flows
• Familiarity with peripheral interfaces like SD/eMMC and (LP)DDR
• Familiarity with simulation tools such as VCS
• Familiarity with laboratory equipment such as Oscilloscopes, Protocol-Analyzers

Travelling:

As a worldwide organization there is sometimes short term travel maybe required.

The Team You’ll Be a Part Of:

You will be joining the FPGA Design and Verification IP Prototyping team, a group of innovative engineers dedicated to building FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs. The team plays a pivotal role in supporting Synopsys' IP business by validating key features, mitigating ASIC potential faults early, and ensuring compliance with industry standards. Collaboration and continuous learning are at the heart of the team, offering a stimulating, challenging, and rewarding environment with positive career development opportunities.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

XML job scraping automation by YubHub

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

You Are:

You are an accomplished engineering professional with a strong background in analog and mixed-signal circuit design. With over 12 years of industry experience, you have a deep understanding of circuit design fundamentals, device physics, and technology effects. You have successfully managed projects from specifications to silicon, and you are comfortable interfacing with both internal and external stakeholders. You are a proactive team player with excellent problem-solving skills and a knack for managing complex projects. Your high energy and flexible personality allow you to go the extra mile, fostering collaboration and driving projects to successful completion. You are adept at conflict resolution and possess strong customer-facing skills, making you an invaluable asset to any high-performing team.

What You’ll Be Doing:

Managing analog and mixed-signal IP projects from specifications to silicon. Interacting with customers to guide them and help adapt our solutions to their needs. Handling customer queries and debugging problems efficiently. Aligning with and improving established design processes. Interfacing with internal and external stakeholders to ensure high engagement levels. Collaborating with a global team to co-develop Analog Full Custom IPs such as GPIOs, I2C, I3C, SMBUS, eMMC, SVID, Quad SPI, JTAG, and more.

The Impact You Will Have:

Driving the integration of advanced capabilities into System on Chips (SoCs). Enabling customers to meet unique performance, power, and size requirements. Accelerating the time-to-market for differentiated products with reduced risk. Enhancing the design and development of high-performance silicon IP. Improving customer satisfaction through efficient problem-solving and support. Contributing to the continuous innovation and technological advancements at Synopsys.

What You’ll Need:

Bachelor's or Master's degree in Electrical Engineering or a related field from a reputed institution. 12+ years of industry experience in analog and mixed-signal circuit design. Proven experience in managing projects from specifications to silicon. Strong understanding of circuit design fundamentals, device physics, and technology effects. Proficiency in spice simulations and various sub-micron design methodologies.

Who You Are:

A proactive team player with strong written and verbal communication skills. High energy individual with the ability to go the extra mile. Creative and flexible personality with excellent customer-facing skills. Demonstrates good analysis and problem-solving skills. Adept at conflict resolution and fostering collaboration among team members.

The Team You’ll Be A Part Of:

You will be part of a strong development team specializing in GPIOs, Specialty IOs, and General Purpose Analog IPs. The team is distributed globally, bringing together experienced professionals from various sites. Together, you will co-develop high-performance analog full custom IPs and work on projects that push the boundaries of technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

XML job scraping automation by YubHub