{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/emir"},"x-facet":{"type":"skill","slug":"emir","display":"Emir","count":12},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_63c3f231-21b"},"title":"Analog Layout Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>As an experienced Analog Layout Senior Engineer, you will work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees. You will floor plan, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics. You will apply Analog Layout techniques to ensure design meets performance with minimum area and good yield. You will build and enhance layout flow for faster, higher quality design processes.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees.</li>\n<li>Floor plan, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics.</li>\n<li>Apply Analog Layout techniques to ensure design meets performance with minimum area and good yield.</li>\n<li>Build and enhance layout flow for faster, higher quality design processes.</li>\n<li>Perform layout verification for DRC/LVS/ERC/ANT/ESD/DFM.</li>\n<li>Conduct PERC verification for ESD/LUP checks.</li>\n<li>Complete all design quality checks and data quality checks.</li>\n<li>Collaborate with Place and Route engineers to integrate analog layouts into the top level.</li>\n<li>Work with the Package team to ensure the integration of top die and package.</li>\n<li>Participate in design reviews across the global team.</li>\n<li>Engage in package design, including interposer and RDL design.</li>\n<li>Collaborate closely with design teams in Vietnam, USA, Canada, and other countries to ensure the success of the whole product.</li>\n<li>Join research programs to implement new ideas for future products and flows.</li>\n<li>Lead a layout team to complete a full design block.</li>\n<li>Mentor junior layout engineers or interns.</li>\n</ul>\n<p><strong>Impact</strong></p>\n<ul>\n<li>Drive the development of high-performance Analog IPs that power cutting-edge technologies.</li>\n<li>Enhance the layout design process for improved efficiency and quality.</li>\n<li>Ensure the robustness and reliability of our designs through meticulous verification processes.</li>\n<li>Contribute to the integration of complex layouts into top-level designs.</li>\n<li>Foster collaboration and knowledge sharing across global teams.</li>\n<li>Mentor and develop the next generation of layout engineers.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>BS in Electronics Engineering, Electromechanics, Telecommunications.</li>\n<li>2+ years of experience in custom layout.</li>\n<li>Proficiency with layout entry tools: Cadence, Synopsys.</li>\n<li>Experience with layout verification tools: Mentor Calibre, Synopsys ICV.</li>\n<li>Understanding of basic semiconductor fabrication processes and MOSFET fundamentals.</li>\n<li>Knowledge of high-speed layout techniques, ESD, Latchup, Antenna, EMIR.</li>\n<li>Experience mentoring/leading junior layout engineers.</li>\n<li>Ability to write layout review presentations and layout verification reports.</li>\n<li>Good English communication skills.</li>\n</ul>\n<p><strong>Team</strong></p>\n<p>You will join a dynamic and innovative team focused on developing high-performance Analog IPs. Our team collaborates closely with colleagues in Vietnam, USA, Canada, and other countries to ensure the success of our products. We value teamwork, knowledge sharing, and continuous improvement, and we are committed to fostering a supportive and inclusive work environment.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_63c3f231-21b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/analog-layout-design-sr-engineer/44408/92879619712","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Cadence","Synopsys","Mentor Calibre","Synopsys ICV","Electronics Engineering","Electromechanics","Telecommunications","High-speed layout techniques","ESD","Latchup","Antenna","EMIR"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:34.005Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Cadence, Synopsys, Mentor Calibre, Synopsys ICV, Electronics Engineering, Electromechanics, Telecommunications, High-speed layout techniques, ESD, Latchup, Antenna, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7c858523-91f"},"title":"SOC Engineering, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.</p>\n<p>Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n<li>Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n<li>Support strategic customer engagements and help expand Synopsys&#39; presence in the semiconductor ecosystem through successful project outcomes.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.</li>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).</li>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimisation, STA, EMIR, and physical verification.</li>\n<li>Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.</li>\n<li>Strong scripting and automation skills using Python, PERL, TCL, or similar languages.</li>\n<li>Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.</li>\n<li>Exposure to high-frequency design and low-power design methodologies.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Proactive, self-motivated, and driven to achieve technical excellence.</li>\n<li>Exceptional problem-solving and analytical skills with a keen attention to detail.</li>\n<li>Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.</li>\n<li>Collaborative team player who values knowledge sharing and mentoring others.</li>\n<li>Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</p>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>** Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7c858523-91f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-engineering-staff-engineer/44408/92684730800","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimisation","static timing analysis (STA)","physical verification","block-level and full-chip floor-planning","EMIR analysis","timing closure","Python","PERL","TCL","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime"],"x-skills-preferred":["high-frequency design","low-power design methodologies","collaboration","problem-solving","analytical skills","communication","interpersonal abilities"],"datePosted":"2026-04-05T13:22:21.047Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimisation, static timing analysis (STA), physical verification, block-level and full-chip floor-planning, EMIR analysis, timing closure, Python, PERL, TCL, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, high-frequency design, low-power design methodologies, collaboration, problem-solving, analytical skills, communication, interpersonal abilities"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_471316cf-932"},"title":"Analog Layout, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are hiring a Staff Engineer to lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.</p>\n<p>As a Staff Engineer, you will be responsible for leading the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies. You will work on hands-on execution of layout development, ensuring precision and adherence to industry standards.</p>\n<p>You will also mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.</p>\n<p>Estimating project efforts, planning schedules, and executing projects in cross-functional settings will be another key responsibility.</p>\n<p>Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks will also be a part of your role.</p>\n<p>Managing the release process, ensuring timely delivery and consistent quality of layout deliverables will be your additional responsibility.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li><p>Lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.</p>\n</li>\n<li><p>Hands-on execution of layout development, ensuring precision and adherence to industry standards.</p>\n</li>\n<li><p>Mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.</p>\n</li>\n<li><p>Estimating project efforts, planning schedules, and executing projects in cross-functional settings.</p>\n</li>\n<li><p>Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.</p>\n</li>\n<li><p>Managing the release process, ensuring timely delivery and consistent quality of layout deliverables.</p>\n</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li><p>BTech/MTech degree in Electrical Engineering, Electronics, or related field.</p>\n</li>\n<li><p>5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).</p>\n</li>\n<li><p>Expertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.</p>\n</li>\n<li><p>Strong understanding of floorplan techniques and deep submicron effects.</p>\n</li>\n<li><p>Proven ability to lead projects and deliver best product quality within tight timelines.</p>\n</li>\n</ul>\n<p>Preferred Qualifications:</p>\n<ul>\n<li><p>Collaborative and team-oriented, with a commitment to inclusion and diversity.</p>\n</li>\n<li><p>Detail-oriented, with strong problem-solving and analytical skills.</p>\n</li>\n<li><p>Effective communicator, both written and verbal, with excellent interpersonal abilities.</p>\n</li>\n<li><p>Adaptable and eager to learn, embracing new technologies and methodologies.</p>\n</li>\n<li><p>Empathetic mentor, fostering accountability, ownership, and technical growth in others.</p>\n</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li><p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n</li>\n<li><p>In addition to company holidays, we have ETO and FTO Programs.</p>\n</li>\n<li><p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n</li>\n<li><p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n</li>\n<li><p>Save for your future with our retirement plans that vary by region and country.</p>\n</li>\n<li><p>Competitive salaries.</p>\n</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_471316cf-932","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/analog-layout-staff-engineer/44408/92693931728","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","CMOS","FinFET","GAA process technologies","layout matching techniques","ESD","latch-up","PERC","EMIR","DFM","LEF generation","bond-pad layout","IO frame and pitch requirements"],"x-skills-preferred":["collaborative and team-oriented","detail-oriented","effective communicator","adaptable and eager to learn","empathetic mentor"],"datePosted":"2026-04-05T13:21:26.995Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, CMOS, FinFET, GAA process technologies, layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements, collaborative and team-oriented, detail-oriented, effective communicator, adaptable and eager to learn, empathetic mentor"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_41cabece-785"},"title":"Layout Design, Sr Supervisor","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a visionary leader and seasoned layout design professional, passionate about advancing the frontiers of semiconductor technology. With over eight years of hands-on experience, you thrive in dynamic environments where innovation and technical excellence are paramount.</p>\n<p>You possess a deep understanding of deep submicron effects, advanced floorplanning techniques, and process technologies like CMOS, FinFET, and GAA at 7nm and below. Your expertise extends to layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, and IO frame and pitch requirements.</p>\n<p>You are adept at leading multi-disciplinary teams, creating an environment of accountability, ownership, and growth, while mentoring junior engineers and empowering senior team members to excel.</p>\n<p>You value diversity and inclusion, fostering a culture where every voice is heard and respected. Your collaborative approach ensures seamless cross-functional coordination, and you have a knack for translating complex technical requirements into actionable project plans.</p>\n<p>Your communication skills,both written and verbal,enable you to engage effectively with stakeholders at all levels. You are motivated by the opportunity to contribute to high-impact projects, drive innovation in DDR/HBM PHY IP layout, and deliver differentiated products that shape the industry.</p>\n<p>If you are ready to lead, inspire, and make a lasting impact, Synopsys is the place for you.</p>\n<p>Leading the development of next-generation DDR/HBM IP layouts, driving technical innovation and quality excellence.</p>\n<p>Mentoring and managing a team of layout engineers, fostering growth and maximizing individual and team potential.</p>\n<p>Developing and maintaining project schedules, ensuring timely delivery while balancing technical and resource constraints.</p>\n<p>Collaborating cross-functionally with design, verification, and IP teams to align on project requirements and execution.</p>\n<p>Providing subject matter expertise in high-speed DDR/HBM IP layout, including floorplanning, layout reviews, and quality checks.</p>\n<p>Executing layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO requirement analysis.</p>\n<p>Supporting layout automation through scripting and tool enhancement, optimizing efficiency and productivity.</p>\n<p>Acting as an advisor to resolve project challenges and guide teams towards innovative solutions.</p>\n<p>Accelerating the integration of advanced capabilities into SoCs, helping customers achieve unique performance, power, and size targets.</p>\n<p>Reducing time-to-market and risk for differentiated products through robust layout design and technical leadership.</p>\n<p>Driving continuous improvement in layout methodologies and quality standards across cross-functional teams.</p>\n<p>Empowering your team to deliver high-performance DDR/HBM PHY IPs that set industry benchmarks.</p>\n<p>Fostering a collaborative, inclusive work environment that values innovation, accountability, and diversity.</p>\n<p>Contributing to Synopsys’ reputation as the provider of the world’s broadest portfolio of silicon IP.</p>\n<p>Shaping the future of chip design and verification technologies through your expertise and leadership.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_41cabece-785","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-supervisor/44408/93269033008","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["deep submicron effects","advanced floorplanning techniques","CMOS","FinFET","GAA","layout matching","ESD","latch-up","PERC","EMIR","DFM","LEF generation","bond-pad layout","IO frame and pitch requirements"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:15.106Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"deep submicron effects, advanced floorplanning techniques, CMOS, FinFET, GAA, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_46c163f2-a81"},"title":"R&D Engineering, Staff Engineer - Physical Design CAD","description":"<p>You will be working at Synopsys, a leading provider of electronic design automation (EDA) software and services. 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You will also support project execution by troubleshooting timing, congestion, and physical verification challenges.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Driving RTL-to-GDSII implementation for complex digital IP, ensuring signoff timing and PV closure.</li>\n<li>Leading backend flow development, including PnR, STA, DRC, LVS, and EMIR analysis.</li>\n<li>Collaborating with design, CAD, and cross-functional teams to optimize backend methodologies and resolve technical issues.</li>\n<li>Supporting project execution by troubleshooting timing, congestion, and physical verification challenges.</li>\n</ul>\n<p>You will be part of the dynamic Design Support Group (DSG) at Synopsys, a passionate collective of engineers dedicated to delivering world-class backend solutions. Our team thrives on innovation, collaboration, and a shared commitment to technical excellence. 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Our team is at the forefront of memory IP solutions, working collaboratively to deliver robust, high-performance SRAM products for a diverse range of applications. We foster a culture of innovation, knowledge sharing, and continuous improvement, empowering each member to contribute to the advancement of cutting-edge technologies in semiconductor design.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_937c266a-1fb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/sram-design-engineer-staff/44408/91675562416","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["CMOS-based block level circuit design","SRAM architectures","digital circuit design","VLSI process concepts","scripting languages","EDA tools","SRAM circuit design","bitcell analysis","design criteria development"],"x-skills-preferred":["Python","Tcl/Tk","Perl","Unix shell","XA","Hspice","Verilog","Starrc","EMIR"],"datePosted":"2026-03-09T11:02:55.213Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"CMOS-based block level circuit design, SRAM architectures, digital circuit design, VLSI process concepts, scripting languages, EDA tools, SRAM circuit design, bitcell analysis, design criteria development, Python, Tcl/Tk, Perl, Unix shell, XA, Hspice, Verilog, Starrc, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_dfb98ecf-dd6"},"title":"Engineering Architect (Analog Mixed-Signal Architect)","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15195</p>\n<p><strong>Base Salary Range</strong></p>\n<p>$181000-$272000</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/16/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>You will be responsible for independently owning and driving full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</p>\n<ul>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n</ul>\n<ul>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.</li>\n</ul>\n<ul>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).</li>\n</ul>\n<ul>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimization, STA, EMIR, and physical verification.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2979db56-dec","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/soc-engineering-staff-engineer-physical-design/44408/91188492080","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","CTS","timing optimization","STA","EMIR","physical verification"],"x-skills-preferred":["Python","PERL","TCL"],"datePosted":"2026-02-04T16:17:00.859Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, CTS, timing optimization, STA, EMIR, physical verification, Python, PERL, TCL"}]}