{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/emir-power-signoff"},"x-facet":{"type":"skill","slug":"emir-power-signoff","display":"EMIR/Power signoff","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8bdc9e27-30e"},"title":"Staff Engineer - Physical Design & Signoff (Synthesis to GDS2)","description":"<p>You will conceptualize, design, and productize state-of-the-art RTL to GDS implementation for SLM monitors using ASIC design flows.</p>\n<p>Design on-chip Process, Voltage, Temperature, glitch, and Droop monitors for silicon biometrics and reliability.</p>\n<p>Execute digital backend activities, including synthesis, pre-layout STA, SDC constraints development, floor planning, bump placement, power planning, MV design techniques, VCLP, UPF understanding, placement, CTS, and routing.</p>\n<p>Drive post-layout STA, timing and functional ECO development, and timing signoff methodology for high-frequency IP design closure.</p>\n<p>Perform physical verification tasks such as DRC, LVS, PERC, ERC, Antenna, EMIR, and Power signoff.</p>\n<p>Collaborate with architects and circuit design engineering teams to create and refine new flows and methodologies.</p>\n<p>Ensure pre-layout and post-layout timing closure and timing model characterizations across various design corners, meeting reliability and aging requirements for automotive and consumer products.</p>\n<p>Accelerating the integration of next-generation intelligent in-chip sensors and analytics into Synopsys technology products.</p>\n<p>Optimizing performance, power, area, schedule, and yield at every stage of the semiconductor lifecycle.</p>\n<p>Enhancing product reliability and differentiation in the market, reducing risk for customers and partners.</p>\n<p>Driving innovation in physical design, verification, STA, and signoff methodologies and tools.</p>\n<p>Contributing to industry-leading SLM monitors and silicon biometrics solutions that set new standards.</p>\n<p>Collaborating with cross-functional teams to ensure successful deployment and adoption of advanced technologies.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8bdc9e27-30e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/staff-engineer-physical-design-and-signoff-synthesis-to-gds2/44408/94244068752","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Physical Design","Physical Verification","pre- & post-layout STA","EMIR/Power signoff","SDC development","UPF/Multivoltage design","DRC","LVS","DFM cleaning","Timing closure","Digital design tools","Synopsys tools"],"x-skills-preferred":["Advanced nodes","Scripting (TCL/PERL)","Custom methodologies","Flow enhancements"],"datePosted":"2026-04-24T14:13:55.186Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Design, Physical Verification, pre- & post-layout STA, EMIR/Power signoff, SDC development, UPF/Multivoltage design, DRC, LVS, DFM cleaning, Timing closure, Digital design tools, Synopsys tools, Advanced nodes, Scripting (TCL/PERL), Custom methodologies, Flow enhancements"}]}