We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.

Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.
• Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.
• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.
• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.
• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.
• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.
• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

What You’ll Need:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimisation, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.
• Exposure to high-frequency design and low-power design methodologies.

Who You Are:

• Proactive, self-motivated, and driven to achieve technical excellence.
• Exceptional problem-solving and analytical skills with a keen attention to detail.
• Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.
• Collaborative team player who values knowledge sharing and mentoring others.
• Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.

The Team You’ll Be A Part Of:

You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

In addition to company holidays, we have ETO and FTO Programs.

• Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

• Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

XML job scraping automation by YubHub

Key responsibilities include:

• Driving RTL-to-GDSII implementation for complex digital IP, ensuring signoff timing and PV closure.
• Leading backend flow development, including PnR, STA, DRC, LVS, and EMIR analysis.
• Collaborating with design, CAD, and cross-functional teams to optimize backend methodologies and resolve technical issues.
• Supporting project execution by troubleshooting timing, congestion, and physical verification challenges.

You will be part of the dynamic Design Support Group (DSG) at Synopsys, a passionate collective of engineers dedicated to delivering world-class backend solutions. Our team thrives on innovation, collaboration, and a shared commitment to technical excellence. We work closely with customers and internal teams, supporting them through every stage of their design journey and continually pushing the boundaries of what's possible in digital backend technology.

As a Staff Engineer, you will have the opportunity to work on cutting-edge projects, develop your technical skills, and contribute to the growth and success of the company. You will be part of a dynamic and supportive team that values innovation, collaboration, and technical excellence.

XML job scraping automation by YubHub

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15195

Base Salary Range

$181000-$272000

Remote Eligible

No

Date Posted

02/16/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished engineering leader with a passion for advancing the frontiers of analog mixed-signal technology. With a deep understanding of memory and die-to-die interfaces, you thrive in environments where innovation meets real-world impact. You have a proven track record of architecting high-performance solutions, particularly in the realm of High Bandwidth Memory (HBM) interface design. You are committed to continuous learning, keeping pace with evolving technologies and industry trends. Your communication skills enable you to articulate ideas clearly and work effectively across sites and disciplines. Above all, you are driven by the opportunity to contribute to critical components powering AI systems, knowing your work has a lasting impact on the future of technology.

What You’ll Be Doing:

• Reviewing and integrating the latest multichip and interposer technologies from various foundries into Synopsys’ HBM PHY products.

• Defining bump maps and top-level floorplans for HBM PHY products to ensure optimal performance, power, and area (PPA).

• Collaborating with layout teams to deliver top metal covercells optimized for performance and reliability in HBM PHY designs.

• Working with layout and SIPI teams to design interposer geometries that maximize performance and signal integrity.

• Mentoring junior engineers and providing technical guidance across multi-site teams.

The Impact You Will Have:

• Elevate the performance and reliability of Synopsys’ HBM PHY products, directly contributing to the advancement of AI and high-performance computing systems.

• Enable successful integration of cutting-edge multichip and interposer technologies, ensuring Synopsys remains at the forefront of semiconductor innovation.

• Improve manufacturability and scalability of memory interface IPs, supporting the needs of leading semiconductor companies worldwide.

• Drive technical excellence across cross-functional teams, fostering collaboration and knowledge sharing.

• Enhance customer satisfaction by delivering robust, high-quality solutions that meet demanding market requirements.

• Support Synopsys’ reputation as a trusted IP provider through leadership, innovation, and problem-solving.

What You’ll Need:

• MS or PhD in Electrical Engineering or related field.

• 15+ years of experience in memory or die-to-die interface design.

• Expertise in floorplan optimization for IPs integrating full-custom analog and synthesized digital blocks.

• Strong experience with power grid design and EMIR analysis.

• Proficiency in interposer design and implementation.

• Solid understanding of analog principles and designs (bandgaps, LDO regulators, current mirrors, DLL/PLLs).

• Deep knowledge of signal-integrity and power integrity principles.

• Experience with layout impact on circuit performance and reliability.

• Ability to troubleshoot and debug memory interfaces effectively.

• Excellent communication and collaboration skills across multi-site teams.

Who You Are:

• A collaborative leader who inspires and guides teams to technical excellence.

• Detail-oriented, analytical, and able to balance multiple priorities.

• Innovative thinker, open to new approaches and emerging technologies.

• Effective communicator, capable of translating complex technical concepts for diverse audiences.

• Resilient and proactive in addressing challenges and driving solutions.

• Committed to continuous learning and professional growth.

The Team You’ll Be A Part Of:

You’ll join our High Bandwidth Memory interface design team, a group of passionate engineers dedicated to developing best-in-class IP for the world’s most advanced computing systems. Our team collaborates across multiple sites and disciplines, leveraging expertise in analog mixed-signal design, layout, and signal integrity to deliver innovative solutions that power the next generation of AI and high-performance devices.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

XML job scraping automation by YubHub