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YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d01f9436-f2a"},"title":"R&D Engineering, Sr Staff Engineer","description":"<p>You are a highly skilled and knowledgeable professional with a passion for applied digital security of HW and SW implementations. With a PhD or advanced MS degree in Electrical Engineering or Computer Sciences, you bring profound expertise in implementations of cryptography and embedded security. You are an expert in side-channel and fault injection analysis and countermeasure development, and you are experienced with physical security evaluations.</p>\n<p>Your excellent presentation and communication skills enable you to interact effectively across teams and at various levels within the organisations. You thrive in collaborative environments, always ready to help others succeed.</p>\n<p><strong>Key Responsibilities:</strong></p>\n<ul>\n<li>Designing, optimising and testing physical security architectures (and SW) for cryptographic implementations across all Security IP products.</li>\n</ul>\n<ul>\n<li>Coordinating with Security IP product development teams for in-depth and effective physical security assessment, and deployment of countermeasures.</li>\n</ul>\n<ul>\n<li>Coordinating, preparing and driving validation and certification projects for security IP products by external evaluation labs.</li>\n</ul>\n<ul>\n<li>Providing consulting to R&amp;D and management on security risk analysis of security IP products and giving input for product road maps.</li>\n</ul>\n<p><strong>Impact:</strong></p>\n<ul>\n<li>Improving the overall physical attack resistance of our security IP modules, mitigating known and unknown risks and threats.</li>\n</ul>\n<ul>\n<li>Obtaining product security certifications which demonstrate the quality and security of our security IP products to customers.</li>\n</ul>\n<ul>\n<li>Further driving the successful adoption of an overall physical security mindset in the security IP R&amp;D teams and contributing to product development through collaborative input and valuable feedback.</li>\n</ul>\n<ul>\n<li>Establishing and elevating Synopsys&#39; market position as a leader in security IP product.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>PhD degree (equivalent by experience) in Electrical Engineering, Computer Science, or a related field, with 5+ years of relevant working experience.</li>\n</ul>\n<ul>\n<li>In-depth knowledge of and experience in digital security implementations (and SW) in the broad sense.</li>\n</ul>\n<ul>\n<li>Hands-on experience with side-channel attacks and countermeasures, and fault-injection analysis and countermeasures.</li>\n</ul>\n<ul>\n<li>Advanced understanding of practical modern cryptography and cryptographic standards.</li>\n</ul>\n<ul>\n<li>Prior experience with validation and certification projects by evaluation labs is a plus.</li>\n</ul>\n<ul>\n<li>Experience with RTL development, embedded SW development and FPGA-based prototyping is a plus.</li>\n</ul>\n<p><strong>Team:</strong></p>\n<p>The security engineering team is part of the Security IP group which offers market-leading products and solutions for embedded security applications. You will be part of a worldwide dedicated sub-team focusing on physical security of all Security IP products.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d01f9436-f2a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/eindhoven/r-and-d-engineering-sr-staff-engineer/44408/92727418144","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["digital security","cryptography","embedded security","side-channel attacks","fault injection analysis","countermeasure development","physical security evaluations","RTL development","embedded SW development","FPGA-based prototyping"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:59.048Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Eindhoven"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"digital security, cryptography, embedded security, side-channel attacks, fault injection analysis, countermeasure development, physical security evaluations, RTL development, embedded SW development, FPGA-based prototyping"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e31a2c4e-190"},"title":"ASIC Firmware Engineer, Modeling","description":"<p><strong>Job Posting</strong></p>\n<p><strong>ASIC Firmware Engineer, Modeling</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$226K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team</strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong>About the Role</strong></p>\n<p>We are looking for an embedded engineer to help build firmware and associated modeling software for OpenAI’s in house AI accelerator. This role involves designing and developing drivers and functional models for a large array of HW components, writing high throughput and low latency firmware code, investigating bring-up and production issues.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Design and implement drivers for hardware peripherals, including those related to AI chips.</li>\n</ul>\n<ul>\n<li>Design and implement functional software models to simulate SoC uncore logic and enable FW testing against the model</li>\n</ul>\n<ul>\n<li>Design and implement low-latency and high throughput embedded SW to manage HW resources.</li>\n</ul>\n<ul>\n<li>Work with adjacent software and hardware teams to implement requirements, debug issues and shape future generations of the hardware.</li>\n</ul>\n<ul>\n<li>Collaborate with vendors to integrate their technologies within our systems.</li>\n</ul>\n<ul>\n<li>Bring up and debug firmware/driver on new platforms.</li>\n</ul>\n<ul>\n<li>Come up with processes and debug issues raised in the field.</li>\n</ul>\n<ul>\n<li>Set up monitoring, integration testing and diagnostics tools.</li>\n</ul>\n<p><strong>Qualifications</strong></p>\n<ul>\n<li>5+ years of experience working in embedded SW space.</li>\n</ul>\n<ul>\n<li>Ability to thrive in ambiguity and learn new technologies.</li>\n</ul>\n<ul>\n<li>Strong programming skills in C/C++ and/or Rust.</li>\n</ul>\n<ul>\n<li>Experience developing high throughput, low latency and multi-threaded code.</li>\n</ul>\n<ul>\n<li>Experience working with real time operating systems (RTOS).</li>\n</ul>\n<ul>\n<li>Experience developing hardware drivers and working with hardware</li>\n</ul>\n<ul>\n<li>Experience with HW/SW co-design</li>\n</ul>\n<ul>\n<li>Knowledge of common embedded protocols, e.g. UART, I2C, SPI, etc.</li>\n</ul>\n<ul>\n<li>Knowledge of microprocessor and common ARM architectures (e.g. AMBA) is a plus.</li>\n</ul>\n<ul>\n<li>Knowledge of PCIe, ethernet and other high BW communication protocols is a plus.</li>\n</ul>\n<ul>\n<li>Experience with GPUs or other compute hardware is a plus.</li>\n</ul>\n<ul>\n<li>Experience deploying large compute clusters is a plus.</li>\n</ul>\n<p>_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e31a2c4e-190","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/e4ef18a1-f2f7-4920-a53c-aeadd184d124","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$226K – $445K • Offers Equity","x-skills-required":["C/C++","Rust","Embedded SW","Real time operating systems (RTOS)","Hardware drivers","HW/SW co-design","Common embedded protocols (UART, I2C, SPI, etc.)","Microprocessor and common ARM architectures (e.g. AMBA)","PCIe, ethernet and other high BW communication protocols"],"x-skills-preferred":["GPU","Compute hardware","Large compute clusters"],"datePosted":"2026-03-06T18:40:36.430Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"C/C++, Rust, Embedded SW, Real time operating systems (RTOS), Hardware drivers, HW/SW co-design, Common embedded protocols (UART, I2C, SPI, etc.), Microprocessor and common ARM architectures (e.g. AMBA), PCIe, ethernet and other high BW communication protocols, GPU, Compute hardware, Large compute clusters","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":226000,"maxValue":445000,"unitText":"YEAR"}}}]}