Job Description

As an experienced Analog Layout Senior Engineer, you will work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees. You will floor plan, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics. You will apply Analog Layout techniques to ensure design meets performance with minimum area and good yield. You will build and enhance layout flow for faster, higher quality design processes.

Responsibilities

• Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees.
• Floor plan, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics.
• Apply Analog Layout techniques to ensure design meets performance with minimum area and good yield.
• Build and enhance layout flow for faster, higher quality design processes.
• Perform layout verification for DRC/LVS/ERC/ANT/ESD/DFM.
• Conduct PERC verification for ESD/LUP checks.
• Complete all design quality checks and data quality checks.
• Collaborate with Place and Route engineers to integrate analog layouts into the top level.
• Work with the Package team to ensure the integration of top die and package.
• Participate in design reviews across the global team.
• Engage in package design, including interposer and RDL design.
• Collaborate closely with design teams in Vietnam, USA, Canada, and other countries to ensure the success of the whole product.
• Join research programs to implement new ideas for future products and flows.
• Lead a layout team to complete a full design block.
• Mentor junior layout engineers or interns.

Impact

• Drive the development of high-performance Analog IPs that power cutting-edge technologies.
• Enhance the layout design process for improved efficiency and quality.
• Ensure the robustness and reliability of our designs through meticulous verification processes.
• Contribute to the integration of complex layouts into top-level designs.
• Foster collaboration and knowledge sharing across global teams.
• Mentor and develop the next generation of layout engineers.

Requirements

• BS in Electronics Engineering, Electromechanics, Telecommunications.
• 2+ years of experience in custom layout.
• Proficiency with layout entry tools: Cadence, Synopsys.
• Experience with layout verification tools: Mentor Calibre, Synopsys ICV.
• Understanding of basic semiconductor fabrication processes and MOSFET fundamentals.
• Knowledge of high-speed layout techniques, ESD, Latchup, Antenna, EMIR.
• Experience mentoring/leading junior layout engineers.
• Ability to write layout review presentations and layout verification reports.
• Good English communication skills.

Team

You will join a dynamic and innovative team focused on developing high-performance Analog IPs. Our team collaborates closely with colleagues in Vietnam, USA, Canada, and other countries to ensure the success of our products. We value teamwork, knowledge sharing, and continuous improvement, and we are committed to fostering a supportive and inclusive work environment.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a UCIe Analog Design Senior Engineer at Synopsys, you will design circuit for Analog IPs like High Speed IOs, LCDL, Bandgap, High Speed macros for high speed PHY, Clock trees, Calibration circuits...

You will analyze and verify to make sure design meet all requirements of functionality, performance, area and reliability.

You will work closely with layout engineers to make sure layout quality. Perform post layout verifications.

You will perform design characterizations, functionality checks, EMIR analysis, Co-simulations for Logic-Analog full chip operations.

You will design analysis and solve problems of noise, margin, signal integrity, power integrity.

You will complete all design quality checks and data quality checks

You will do design reviews across global team

You will work with digital/system engineer to integrate analog designs into mixed signal system. Perform mixed signal verification which combining both analog and digital blocks.

You will train for fresh engineers and interns

The ideal candidate will have a BS/MS in Electronics Engineering, Electromechanics, Telecommunications.

They should have 0-3 years of experience in Analog, Mixed Signal, Memory or Custom logic Circuit design.

They should have solid knowledge of CMOS Analog design knowledge and techniques

They should have solid skill with circuit design tools: SNSP Custom Designer, Cadence Virtuoso

They should have solid understanding circuit simulation tools: Hspice or Spectre or Custom Sim...

They should have good understanding of layout effects on circuit performance.

They should have experienced with writing design review presentations and circuit verification reports

They should have good English communication both verbally and in writing

They should be a great team player, willing to support others.

They should be highly responsible, result oriented.

They should be self-motivated and highly enthusiasm in technology and solving problems

Leadership skill and experience is a plus

Familiar with high speed analog designs, IO designs, PLL/DLL is a plus

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