You will work cross-functionally with internal engineering teams and external ecosystem partners to translate product requirements into scalable silicon solutions, driving execution from concept through delivery.

Key responsibilities include:

• Defining the architecture and technical roadmap for custom SoCs targeted for edge applications.
• Driving system-level tradeoff analysis across compute, memory, interconnect, power, thermal, and cost constraints.
• Architecting energy-efficient ML compute subsystems optimized for inference workloads and real-world deployment environments.
• Collaborating with internal hardware, software, systems, and product teams to align architecture with platform needs.
• Partnering with external silicon vendors, IP providers, and manufacturing partners to execute development plans.
• Leading hardware/software co-design efforts to maximize performance per watt and end-to-end system efficiency.
• Guiding implementation teams through microarchitecture, RTL development, validation, and bring-up phases.

To be successful in this role, you will need:

• Proven experience defining and delivering complex SoC or ASIC architectures from concept to production.
• Deep understanding of AI/ML accelerators, edge inference workloads, and energy-efficient compute design.
• Strong knowledge of SoC subsystems including CPU/GPU/NPU architectures, memory hierarchies, interconnects, and power management.
• Experience working with both internal engineering organizations and external strategic partners.
• Ability to lead cross-functional teams in fast-paced, execution-driven environments.
• Strong communication skills with the ability to influence technical direction across organizations.

Preferred qualifications include experience with edge AI devices, embedded systems, or consumer hardware platforms, background in performance modeling, silicon cost optimization, and workload-driven architecture, and familiarity with advanced process nodes and modern semiconductor development flows.

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