Your responsibilities will include:

• Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
• Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.
• Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
• Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.
• Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.
• Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.
• Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys' technical edge.

You will accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. You will ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. You will drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. You will enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. You will contribute to the development of next-generation verification methodologies and best practices within Synopsys. You will strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

To be successful in this role, you will need:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.
• 5-8 years of hands-on experience in the Physical Verification (PV) domain.
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
• Exposure to competitive EDA tools and awareness of their strengths and limitations.

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

Rewards and benefits include a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We are seeking an accomplished architect with expertise in high-speed analog and mixed-signal IC design. You will thrive on solving complex challenges and leading teams to deliver innovative transceiver solutions for silicon photonics.

Key responsibilities include:

Architecting 224G & 448G analog transceiver solutions for silicon photonics. Collaborating across engineering teams to drive integration and innovation. Mentoring engineers and supporting technical growth. Representing Synopsys in industry forums. Shaping technical roadmaps for emerging markets. Ensuring designs meet stringent performance and reliability standards.

As an Analog Design Architect, you will advance Synopsys' leadership in silicon photonics and high-speed analog design. You will enable next-generation data center and cloud connectivity, drive technical excellence and innovation, promote collaboration and knowledge sharing, influence industry standards, and open new business opportunities.

Requirements include:

Deep experience in high-speed analog/mixed-signal IC and transceiver design. Expertise in 224G & 448G architectures and silicon photonics integration. Proficiency with EDA tools and IC layout. Strong grasp of signal integrity and power management. Ability to translate technical needs into scalable solutions.

Ideal candidates are innovative and collaborative leaders with a clear communication style, detail-oriented and adaptable, and passionate about advancing technology.

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You will develop subject matter expertise and industry knowledge through hands-on projects and collaboration with product development teams. You will translate customer requirements into new product features, test new releases, and develop application best practices. You will support field and digital marketing initiatives, author conference presentations, and contribute to consulting services and training classes.

As an Application Engineer, you will empower customers to solve complex engineering challenges with advanced simulation solutions. You will drive the adoption of Synopsys and Ansys products in customer workflows, expanding business opportunities. You will enhance the product portfolio by translating real-world needs into innovative features. You will establish Synopsys as a trusted partner through expert technical support and consulting.

You will contribute to the growth and reputation of the Customer Excellence team in Japan and beyond. You will advance industry standards by sharing knowledge and best practices in conferences and training sessions.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An experienced and passionate ASIC Digital Design Engineer who thrives in dynamic and collaborative environments. You have a proven track record in RTL design and verification, and you are excited about contributing to cutting-edge technology. With your extensive expertise, you can handle complex and unique issues, often requiring innovative solutions. You are adept at communicating with both internal and external stakeholders, ensuring that your designs meet the highest standards of quality and performance.

What You’ll Be Doing:

• Leading the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.
• Collaborating closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.
• Developing and executing comprehensive test plans to verify the functionality and performance of your designs.
• Utilizing advanced EDA tools and methodologies to optimize design performance and power efficiency.
• Mentoring junior engineers, providing guidance and support to help them grow their skills and contribute effectively to the team.
• Staying up to date with the latest industry trends and technologies, continuously improving your skills and knowledge.

The Impact You Will Have:

• Driving innovation in ASIC design, contributing to the development of cutting-edge technology that shapes the future.
• Ensuring the delivery of high-performance, reliable, and power-efficient ASICs that meet customer requirements and industry standards.
• Enhancing the overall quality and performance of Synopsys' products through meticulous design and verification processes.
• Collaborating with cross-functional teams to solve complex design challenges, ensuring seamless integration and functionality.
• Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement within the team.
• Contributing to Synopsys' reputation as a leader in the semiconductor industry through your expertise and innovative solutions.

What You’ll Need:

• Extensive experience in ASIC digital design and verification, with a strong background in RTL design, using industry standard HDLs; Verilog, SystemVerilog.
• Proficiency in using industry-standard EDA tools and methodologies for design and verification.
• Deep understanding of High-Performance Interface IP protocols and their implementation in ASIC design, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).
• Broad knowledge of the full digital ASIC and IP development flow, including RTL design, lint, CDC, RDC, synthesis and STA.
• Experience with power analysis and RTL level power optimization techniques.
• Familiarity with verification languages and methodologies; SystemVerilog, SVA, UVM.
• Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.
• Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.

Who You Are:

• A proactive and self-motivated individual who takes initiative and acts independently with minimal oversight.
• A strategic thinker with the ability to implement goals that have a direct impact on department results.
• A detail-oriented engineer who works meticulously to ensure the highest standards of quality and performance.
• A collaborative team player who thrives in dynamic and fast-paced environments.
• A lifelong learner who stays up to date with the latest industry trends and continuously seeks to improve their skills and knowledge.

The Team You’ll Be A Part Of:

You will be part of a highly skilled and dynamic ASIC Digital Design team focused on delivering high-performance and reliable ASIC solutions. Our team collaborates closely with various departments, including analog design, physical design, and applications engineering, to ensure the seamless integration of all design components. We are committed to continuous learning and improvement, fostering a culture of innovation and excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

You Are:

You are an Automation Engineer/Software Developer who develops scripts, tools, and workflows to automate routine design tasks, enhancing efficiency, precision, and standardization. With a strong foundation in Software Development lifecycle, Software testing and deployment. You are creating methodologies and documentation for the users you support.

Your problem-solving skills and proficiency in UNIX/Linux and programming languages make you a valuable team player.

Your strong communication skills in English enable you to effectively document methods and training materials, ensuring your team can leverage new tools and flows to increase efficiency. You are proactive in providing feedback to improve internal tools and are committed to streamlining design processes and reducing time-to-market.

What You’ll Be Doing:

• Design, develop, troubleshoot, or debug software tools for integrated circuits.
• Develop automation tools, data pipelines, workflows for Analog design teams, to improve project methodologies and lifecycle efficiency.
• Providing feedback to internal tools teams to enhance tool functionality and usability.
• Documenting methods, creating documentation, and training materials for internal designers.
• Collaborating with cross-functional teams to ensure seamless integration and optimization of design tools.

The Impact You Will Have:

• Ensuring the successful implementation of new design methodologies and tools within the team.

• Enhancing the overall efficiency of analog design processes within Synopsys.

• Reducing time-to-market for high-performance silicon chips and software content.

• Driving innovation by providing valuable feedback to improve internal design tools and flows.

• Contributing to the development of cutting-edge technology that shapes the future of the industry.

What You’ll Need:

• Bachelor’s degree in software engineering/electrical engineering or similar field and 2 years of related experience.
• Experience with OOP languages, Python is preferred.
• Experience with CI/CD tools and workflows.
• Familiarity with UNIX/Linux operating systems and shell scripting,
• Experience with Tcl, Perl, Bash, JavaScript is a plus.
• Experience with latest GenAI tools development is a big plus.
• Experience with EDA tools for schematic entry, physical layout, design verification and circuit simulations is a big plus.
• Prior experience working with VLSI design methodology is big plus.

Who You Are:

• Excellent communication skills in English.
• A team player with a collaborative mindset.
• Proactive in debugging and resolving issues independently.
• Skilled in creating clear and concise documentation.

The Team You’ll Be A Part Of:

You will be part of a dynamic team dedicated to streamlining design processes and reducing time-to-market. This team focuses on developing, testing, improving and training designers on cutting-edge flows and tools at Synopsys to enhance analog design efficiency. Your role will involve significant collaboration with cross-functional teams to foster a culture of continuous improvement and innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.

Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.
• Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.
• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.
• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.
• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.
• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.
• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

What You’ll Need:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimisation, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.
• Exposure to high-frequency design and low-power design methodologies.

Who You Are:

• Proactive, self-motivated, and driven to achieve technical excellence.
• Exceptional problem-solving and analytical skills with a keen attention to detail.
• Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.
• Collaborative team player who values knowledge sharing and mentoring others.
• Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.

The Team You’ll Be A Part Of:

You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

In addition to company holidays, we have ETO and FTO Programs.

• Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

• Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

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As a Senior Staff Engineer in RTL Design and Verification, you will be designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects. You will develop comprehensive test cases to ensure robust product functionality and performance.

You will collaborate with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis. You will stay current with emerging trends, standards, and best practices in SLM and 3D-IC technologies.

You will contribute to the improvement of verification methodologies and automation flows. You will document design specifications, verification plans, and results to ensure transparency and repeatability.

You will participate in code reviews and technical discussions to drive innovation and continuous improvement.

You will accelerate the development of industry-leading SLM IPs that power the world's top technology companies. You will enhance product reliability, performance, and user experience for global semiconductor solutions.

You will drive innovation in verification methodologies, setting new standards for efficiency and accuracy. You will enable successful integration of advanced 3D-IC technologies, expanding Synopsys' leadership in the market.

You will foster strong customer relationships through technical expertise and responsive support. You will contribute to a culture of excellence and continuous learning within the engineering team.

To succeed in this role, you will need a BS/MS in Computer Science, Electrical Engineering, or related field. You will require 8+ years of hands-on experience in RTL design and verification.

You will need proficiency in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies. You will need experience working in Unix/Linux environments.

You will need strong debugging and problem-solving skills, especially in complex chip design environments. You will need excellent written and verbal communication skills in English.

Knowledge of digital, analog, and mixed-signal IP/circuit design is a plus. Familiarity with 3D-IC standards and semiconductor verification best practices is desirable.

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Applications Engineering, Sr Engineer

Hsinchu, Taiwan

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Category: EngineeringHire Type: Employee

Job ID 15949Date posted 03/08/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a proactive, customer-oriented engineer passionate about advancing semiconductor technologies. You thrive in fast-paced environments and are eager to solve complex technical challenges, collaborating with leading foundries and design teams. You possess a strong foundation in ASIC design flow, VLSI, and CAD engineering, and are comfortable navigating the intricacies of EDA tools and physical design. Your communication skills enable you to build trust with customers, translating their needs into actionable solutions and ensuring seamless product implementation. You are resourceful, adaptable, and able to exercise sound judgment while tackling technical issues. Your creative approach to problem-solving and drive for excellence enable you to contribute meaningfully to both individual projects and broader team initiatives. You value diversity and inclusivity, and you are committed to continuous learning, staying current with industry trends and emerging technologies. By joining Synopsys, you seek to make a tangible impact on the future of high-performance silicon, and you are motivated by opportunities to grow, innovate, and collaborate in a global, supportive environment.

What You’ll Be Doing:

• Managing and providing ICV runset support for key foundry customers, ensuring optimal product performance and customer satisfaction.

• Delivering post-sales technical expertise during the runset programming, implementation, and maintenance of Synopsys products.

• Implementing detailed customer installation requirements and customizing solutions to fit unique client environments.

• Ensuring client needs are met and that Synopsys solutions function according to technical specifications and industry standards.

• Collaborating with sales teams to provide pre-sales technical support, contributing to successful business development and customer onboarding.

• Troubleshooting and resolving moderately complex technical issues

• Empowering customers to efficiently deploy and maximize the value of Synopsys EDA solutions in their design workflows.

• Enhancing customer satisfaction and strengthening long-term partnerships with key foundry clients.

• Driving successful product adoptions and implementations, contributing directly to Synopsys’ market leadership.

• Supporting the technical excellence of customer projects, enabling innovative chip design and verification outcomes.

• Facilitating knowledge transfer, helping customers understand and leverage advanced product features.

• Identifying opportunities for product improvements and feeding insights back to development teams for continuous innovation.

What You’ll Need:

• Basic understanding of the design process, with a preference for Design Rule Checking (DRC).

• Solid grasp of ASIC design flow, VLSI concepts, and/or CAD engineering principles.

• Familiarity with competitive EDA tool products and expertise in areas such as Verification, Place and Route, Design Reuse, and/or Physical Design.

• Ability to manage projects from initiation through completion, delivering high-quality technical solutions.

• Creative problem-solving skills and the ability to exercise judgment in selecting methods and techniques to obtain solutions.

Who You Are:

• Collaborative and effective communicator, able to build strong relationships with customers and internal teams.

• Resourceful and adaptable, thriving in dynamic, fast-paced environments.

• Detail-oriented with strong analytical skills and a commitment to delivering exceptional results.

• Open-minded and inclusive, embracing diverse perspectives and fostering an environment of belonging.

• Self-motivated and eager to learn, continuously seeking opportunities for growth and innovation.

The Team You’ll Be A Part Of:

You will join the Customer Application Services team, a group of passionate engineers dedicated to delivering technical excellence and customer success. The team works closely with foundries, design teams, and sales professionals, providing deep expertise and support throughout the product lifecycle. You’ll collaborate in a culture of innovation, knowledge sharing, and mutual respect, where every member’s contribution is valued and celebrated.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You are a visionary and detail-oriented principal engineer, passionate about pushing the boundaries of analog circuit design in high-speed interfaces.

With a deep technical foundation and proven leadership skills, you thrive in collaborative environments and are eager to mentor the next generation of engineers.

Your expertise in SerDes and analog macros enables you to dissect complex architectural requirements and translate them into robust, scalable designs.

You are adept at balancing power, area, and performance trade-offs, and you proactively seek innovative solutions to technical challenges.

Your experience spans both the theoretical and practical aspects of circuit design,from transistor-level fundamentals to silicon-proven implementations.

You champion rigorous verification methodologies and leverage advanced simulation tools to ensure the highest quality outcomes.

As a communicator, you clearly articulate your ideas to peers, customers, and junior team members, fostering a culture of learning and excellence.

You are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you approach every project with a commitment to reliability, efficiency, and continuous improvement.

Your adaptability and curiosity make you a valuable contributor to cross-functional teams, and you are excited to make a lasting impact at Synopsys.

Own the architecture, design, and implementation of analog macro-level circuits for SerDes IP.

Track and review the technical progress of sub-block owners, ensuring alignment with project goals.

Interpret SerDes standards and architecture documents to develop detailed analog specifications.

Identify and refine circuit implementations, optimizing for power, area, and performance targets.

Propose and execute design and verification strategies using advanced simulator features for robust outcomes.

Oversee physical layout to minimize parasitics, device stress, and process variation impacts.

Collaborate closely with digital RTL engineers on calibration, adaptation, and control algorithms for analog circuits.

Present simulation data and technical insights for peer and customer reviews.

Mentor and review the progress of junior engineers, fostering growth and technical excellence.

Document design features, methodologies, and test plans for internal and customer use.

Consult on electrical characterization and testing of circuits within the SerDes IP product portfolio.

Drive innovation and quality in Synopsys’ industry-leading SerDes IP solutions.

Elevate the performance and reliability of analog designs, enabling next-generation connectivity standards.

Contribute to the success of global customers by delivering robust, silicon-proven analog macros.

Enhance cross-functional collaboration across design, layout, and digital teams.

Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.

Influence the direction of advanced analog design methodologies and verification strategies.

Provide technical leadership in customer engagements and peer reviews.

Support continuous improvement in design processes and documentation practices.

PhD with 7+ years, or MSc with 10+ years of SerDes/high-speed analog design experience.

Expertise in transistor-level circuit design and strong CMOS design fundamentals.

Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.

Leadership experience in guiding small teams through macro-level design projects.

In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.

Advanced skills in optimizing FinFET CMOS layouts to minimize parasitics and local device mismatches.

Awareness of ESD and reliability issues, including circuit techniques and layout strategies.

Proficiency with EDA tools for schematic entry, physical layout, and design verification.

Experience with SPICE simulators for detailed circuit analysis.

Familiarity with analog behavioral modeling and simulation control using Verilog-A.

Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.

Analytical thinker with exceptional problem-solving skills.

Collaborative leader and effective communicator.

Detail-oriented and methodical in approach.

Adaptable and open to learning new technologies.

Mentor and role model for junior engineers.

Self-motivated and proactive in driving project outcomes.

Committed to excellence, reliability, and innovation.

You will join a dynamic and multidisciplinary team of analog, digital, and mixed-signal engineers dedicated to developing industry-leading SerDes IP solutions.

The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products.

Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce.

We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.

Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a global leader in semiconductor design and verification solutions, we enable the world's most advanced technology companies to deliver cutting-edge SoCs and systems. Our mission is to accelerate innovation through state-of-the-art verification IP, methodologies, and strategic consulting.

You are a passionate and analytical engineer with a proven track record in digital design and verification, ready to embrace the challenge of developing advanced embedded memory test and SLM architectures. You thrive in dynamic, collaborative environments where your technical expertise and innovative mindset can drive significant impact.

You are detail-oriented, always seeking to ensure design integrity and optimal performance through rigorous validation, debugging, and synthesis. Your hands-on approach extends to scripting and automation, enhancing productivity and accelerating development cycles. You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.

Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks. Performing digital design validation and functional verification at both block and SoC levels. Executing logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs. Applying DFT (Design-for-Test) expertise for comprehensive memory and logic testing. Identifying and troubleshooting design timing and DFT functional issues to optimize chip performance. Utilizing and scripting in languages such as Tcl to automate design and verification workflows. Developing and maintaining technical collateral including test suites, protocol documentation, and debug guides.

Accelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies. Shape the evolution of embedded memory test and SLM architectures that power next-generation devices. Drive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products. Enhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support. Contribute to the continuous improvement of Synopsys' design and verification solutions, setting new industry benchmarks. Mentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth. Influence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization. Support strategic decision-making by providing technical insights and market-driven recommendations.

2-4 years of relevant experience in ASIC digital design and verification. Proficiency in RTL simulation, logic synthesis, and timing verification tools. Strong understanding of DFT architectures. Familiarity with debug tools such as Verdi and workflows for performance analysis. Programming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl. Experience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.

Analytical thinker with exceptional problem-solving skills. Effective communicator, able to collaborate across disciplines and with external partners. Proactive, self-motivated, and adaptable in fast-paced environments. Committed to quality, detail, and continuous learning. Team player who values diversity, inclusion, and mentorship. Customer-focused, dedicated to delivering timely and effective solutions.

You'll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. The team bridges R&D, marketing, and customer engagement, driving the roadmap for advanced SoC solutions. With a culture of knowledge sharing, technical excellence, and mutual support, you'll thrive in an environment that values creativity, initiative, and a shared commitment to shaping the future of semiconductor technology.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Principal Engineer in ASIC Digital Design, you will lead the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals. You will collaborate closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.

Key responsibilities include:

• Leading the design and verification of complex ASIC blocks and systems
• Collaborating with cross-functional teams to ensure seamless integration of all design components
• Developing and executing comprehensive test plans to verify the functionality and performance of your designs
• Utilizing advanced EDA tools and methodologies to optimize design performance and power efficiency
• Mentoring junior engineers, providing guidance and support to help them grow their skills and contribute effectively to the team

As a Principal Engineer, you will have a significant impact on the development of cutting-edge technology that shapes the future. You will ensure the delivery of high-performance, reliable, and power-efficient ASICs that meet customer requirements and industry standards.

To succeed in this role, you will need:

• Extensive experience in ASIC digital design and verification, with a strong background in RTL design
• Proficiency in using industry-standard EDA tools and methodologies for design and verification
• Deep understanding of High-Performance Interface IP protocols and their implementation in ASIC designs
• Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges
• Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders

If you are a proactive and self-motivated individual who takes initiative and acts independently with minimal oversight, we encourage you to apply for this exciting opportunity.

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As a High-Speed Interface Digital Design Manager, you will be responsible for managing and mentoring engineers, fostering a culture of innovation, ownership, and continuous improvement. You will drive architecture specification, digital design, and verification activities for current and next-generation products, engaging with customers to manage escalations, facilitate pre- and post-sales discussions, and ensure their requirements are met.

Key responsibilities include:

• Leading a high-performing digital and verification engineering team focused on the design and delivery of advanced SerDes IP
• Managing and mentoring engineers, fostering a culture of innovation, ownership, and continuous improvement
• Driving architecture specification, digital design, and verification activities for current and next-generation products
• Engaging with customers to manage escalations, facilitate pre- and post-sales discussions, and ensure their requirements are met

Requirements include:

• Bachelor's or Master's degree in Electrical Engineering or related field
• 10+ years of hands-on digital design and verification experience in the semiconductor industry
• 5+ years of proven leadership and people management experience, preferably in ASIC or IP development environments
• Deep knowledge of the ASIC development flow, including architecture specification, digital design, and verification methodologies
• Experience with high-speed interface protocols (e.g., PCIe, Ethernet, USB) and digital signal processing techniques
• Expertise in managing customer escalations and facilitating technical discussions during pre- and post-sales phases
• Proficiency with industry-standard EDA tools, scripting, and project management platforms

Benefits include:

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries

If you are a strong leader with excellent team-building and mentoring skills, a customer-focused and results-oriented individual with sound decision-making abilities, a collaborative communicator able to build strong cross-functional alliances, organized, detail-oriented, and adept at managing multiple priorities efficiently, adaptable, proactive, and committed to continuous improvement, we encourage you to apply.

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As a Layout Design Engineer, you will be designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces. You will collaborate with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.

Responsibilities:

• Designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces.
• Collaborating with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.
• Performing floor planning, layout entry, and comprehensive verification to ensure design quality and compliance with foundry rules.
• Applying advanced techniques to mitigate signal integrity issues, ESD, and latch-up risks, including differential routing, shielding, and substrate biasing.
• Optimizing layouts for reliability, matching, and minimizing parasitic effects such as EM and IR drop.
• Supporting design porting activities to enable seamless migration of layouts across multiple foundry nodes and technology platforms.
• Documenting layout methodologies, best practices, and validation results to support knowledge sharing and continuous improvement.

Requirements:

• Bachelor or advanced degree in Electrical or Computer Engineering (or equivalent) with a solid background in transistor-level design.
• 5+ years of experience in analog and mixed-signal CMOS layout design, including complex integrated circuits.
• Expertise in deep submicron CMOS technologies and layout effects (matching, reliability, proximity, EM, IR, etc.).
• Proficiency in layout floor planning, verification, and quality validation using industry-standard EDA tools.
• Strong knowledge of signal integrity, ESD, and latch-up mitigation techniques.
• Familiarity with UNIX operating systems and scripting languages (TCL, Python) is a plus.
• Experience with Synopsys EDA tools is highly desirable.

Who You Are:

• Detail-oriented and quality-focused, with a commitment to delivering robust and reliable designs.
• Excellent communicator, able to articulate technical concepts clearly to diverse audiences.
• Collaborative team player who builds productive relationships and networks effectively.
• Self-motivated, organized, and able to manage multiple priorities in a dynamic environment.
• Strong problem-solving skills and critical judgment, with a proactive approach to overcoming challenges.
• Adaptable and eager to learn new technologies and methodologies.

The Impact You Will Have:

• Accelerate the development of cutting-edge silicon IP, enabling faster integration of advanced capabilities into SoCs.
• Enhance the performance, reliability, and manufacturability of high-speed interface solutions for next-generation applications.
• Reduce time-to-market and risk for customers by delivering high-quality, validated layout designs.
• Contribute to the innovation of analog and mixed-signal design methodologies within a global team.
• Support the creation of differentiated products that power the Era of Smart Everything, from AI to IoT and beyond.
• Foster a culture of collaboration, knowledge sharing, and technical excellence within the team and across the organization.

The Team You'll Be A Part Of:

You will join a dynamic, international team focused on developing high-speed SerDes physical interfaces and supporting analog blocks for advanced SoC solutions. Our team values innovation, collaboration, and technical excellence, working closely with circuit designers, verification engineers, and global partners to deliver industry-leading silicon IP. We foster a supportive environment where knowledge sharing and continuous learning are encouraged, and where your contributions will directly impact the success of our products and customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and detail-oriented engineer who thrives in the fast-paced world of advanced semiconductor layout. You possess a deep understanding of analog and mixed-signal CMOS design principles, with a particular focus on high-speed SerDes interfaces. Your expertise is backed by a solid academic foundation and practical experience, enabling you to tackle complex layout challenges with confidence.

What You’ll Be Doing:

• Drive layout development for high-speed SerDes physical interfaces and complex analog/mixed-signal CMOS blocks.

• Lead the complete layout design process, including floorplanning, verification, and quality assurance, with a strong emphasis on reliability and manufacturability.

• Port designs across multiple foundry nodes, ensuring optimal performance and compliance with technology-specific requirements.

• Implement advanced techniques for signal integrity, ESD, and latch-up mitigation, such as differential routing, shielding, and biasing.

• Collaborate closely with design, verification, and manufacturing teams to deliver robust and scalable layout solutions.

• Utilize Synopsys EDA tools and scripting languages (TCL, Python) to automate layout tasks and optimize workflow efficiency.

The Impact You Will Have:

• Enable Synopsys customers to achieve higher performance and reliability in their silicon designs.

• Accelerate the time-to-market for cutting-edge semiconductor products by delivering high-quality, manufacturable layouts.

• Enhance the robustness and scalability of Synopsys IP through meticulous attention to detail and innovative design solutions.

• Drive advancements in deep submicron CMOS technology adoption and integration.

• Foster a collaborative environment that supports knowledge sharing, mentorship, and professional growth.

• Support Synopsys’ leadership in chip design and verification by contributing to the development of industry-leading IP blocks.

What You’ll Need:

• MSc in Electrical/Computer Engineering (or equivalent).

• Minimum 3 years hands-on experience in analog and mixed-signal CMOS layout, including high-speed SerDes interfaces.

• Deep knowledge of deep submicron CMOS technologies and design for reliability (EM/IR, matching, proximity effects).

• Proficiency in layout floorplanning, porting designs across foundry nodes, and implementing signal integrity and ESD mitigation strategies.

• Experience with custom digital and high-speed digital layout, as well as Synopsys EDA tools.

• Strong skills in UNIX environments, including shell scripting and command-line operations.

• Familiarity with scripting languages such as TCL and Python.

Who You Are:

• Excellent problem-solving, organizational, and communication skills.

• Self-motivated and proactive, with the ability to work independently and as part of a team.

• Effective collaborator who values diverse perspectives and fosters inclusive teamwork.

• Adaptable and open to new challenges, with a commitment to continuous improvement.

• Detail-oriented with a strong sense of ownership and pride in delivering high-quality work.

The Team You’ll Be A Part Of:

You will join a dynamic, highly skilled team dedicated to developing world-class analog and mixed-signal IP for Synopsys’ global customer base. The team is focused on pushing the boundaries of high-speed interface design, reliability, and manufacturability, working together to solve complex challenges and deliver industry-leading solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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We are looking for a passionate, detail-oriented engineer with an insatiable curiosity for technology and its impact on the world. You will thrive in collaborative environments, bringing together diverse perspectives to solve complex challenges. With a strong foundation in RTL design and verification, you will approach every project with a sense of ownership and a commitment to excellence.

As an effective communicator, you will clearly articulate technical concepts to both internal teams and external customers, fostering strong partnerships and driving innovation. You will be adaptable, self-motivated, and resilient in the face of challenges, always seeking opportunities to learn and grow.

Your responsibilities will include designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects. You will develop comprehensive test cases to ensure robust product functionality and performance. You will collaborate with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis.

You will stay current with emerging trends, standards, and best practices in SLM and 3D-IC technologies. You will contribute to the improvement of verification methodologies and automation flows. You will document design specifications, verification plans, and results to ensure transparency and repeatability.

You will participate in code reviews and technical discussions to drive innovation and continuous improvement.

The impact you will have includes accelerating the development of industry-leading SLM IPs that power the world's top technology companies. You will enhance product reliability, performance, and user experience for global semiconductor solutions. You will drive innovation in verification methodologies, setting new standards for efficiency and accuracy.

You will need a BS/MS in Computer Science, Electrical Engineering, or related field. You will have 5+ years of hands-on experience in RTL design and verification. You will be proficient in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies.

You will be an analytical and critical thinker with a detail-oriented approach. You will be an effective communicator, comfortable collaborating across teams and with customers. You will be self-motivated and proactive in seeking solutions and driving projects forward.

You will join a talented and diverse engineering team focused on developing and verifying cutting-edge Silicon Lifecycle Management IPs for next-generation chip solutions.

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As a Sr Staff Application Engineer - VCS Simulation, you will be responsible for leading customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.

Responsibilities

• Lead customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.
• Diagnose and troubleshoot complex technical issues in verification flows, utilizing deep product knowledge and analytical skills.
• Collaborate with global domain experts to gather requirements and contribute to the development of a robust product roadmap.
• Drive competitive engagements by demonstrating Synopsys VCS advantages and supporting customers in benchmarking scenarios.
• Provide technical expertise in HDL/HVL methodologies, including UVM, SVA, and simulation debugging.
• Interface directly with customers, product validation, and R&D teams to propose solutions and suggest improvements in implementation and validation processes.
• Develop and optimize scripts (Perl, TCL, Shell, Make) to enhance productivity and workflow automation.

The Impact You Will Have

• Enable customers to accelerate their verification cycles and achieve first-pass silicon success through expert support and deployment of VCS simulation technology.
• Drive innovation in verification methodologies by integrating advanced features and AI-driven productivity tools.
• Enhance Synopsys' product offerings by providing actionable feedback from customer engagements and competitive benchmarking.
• Facilitate seamless collaboration across global teams, ensuring consistent delivery of high-quality solutions.
• Support the continuous improvement of VCS and related technologies through proactive problem-solving and technical leadership.
• Contribute to the growth of Synopsys' leadership in EDA by empowering customers to leverage the full capabilities of verification platforms.

What You’ll Need

• Bachelor’s degree in Electronics with 7+ years or Master’s degree in Electronics with 5+ years of experience.
• Proficiency in verification technologies, including simulation, UVM, SVA, and LRM.
• Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.
• Proven experience in debugging simulation mismatches and verification flows.
• Advanced scripting skills (Perl, TCL, Make, Shell) and working knowledge of UNIX environments.
• Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.

Who You Are

• Excellent written and oral communication skills, comfortable interfacing with global teams and customers.
• Collaborative team player with a proactive and innovative mindset.
• Detail-oriented and organized, able to manage multiple tasks and priorities.
• Motivated self-starter with strong problem-solving abilities.
• Adaptable and open to travel, eager to learn and grow in a fast-paced environment.

The Team You’ll Be A Part Of

You will join a dynamic and diverse team of applications engineers dedicated to solving the most challenging problems in the verification domain. Our team works at the intersection of technology development, customer engagement, and product innovation, collaborating with experts across field, R&D, and product validation globally. We foster a culture of continuous learning, open communication, and mutual support, ensuring every member can make a meaningful impact and grow professionally.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are an expert in high-speed analog design, with hands-on experience in wireline or optical SerDes above 200GBaud. You excel with PLLs, ILOs, DLLs, and phase mixers, as well as transmitters, serializers, optical drivers, receiver analog front ends, TIAs, and data converters.

Designing advanced SerDes and clocking circuits for ultra-high-speed data. Developing transmitters, serializers, and optical drivers. Creating receiver analog front ends and TIAs. Optimizing signal integrity and power usage. Collaborating across global teams. Mentoring junior engineers.

Enable next-gen connectivity solutions. Strengthen Synopsys' technology leadership. Accelerate product innovation and time-to-market. Improve reliability and performance of industry-leading chips. Foster technical growth across teams. Influence industry standards.

Our ideal candidate has a BSEE with at least 8+ years of direct industry experience. They must have extensive analog/SerDes IC design experience above 200GBaud, expertise with PLLs, DLLs, ILOs, phase mixers, and related circuits, proficiency in EDA tools and advanced process technologies, strong signal integrity and layout skills, and lab validation and debugging experience.

Collaborative and proactive leader. Detail-oriented problem solver. Effective technical communicator. Innovative and curious. Supportive mentor.

Join an elite analog design team focused on high-speed connectivity and SerDes IP, collaborating globally to deliver breakthrough solutions.

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Your primary focus will be on analyzing automated test execution results, investigating anomalies, and reporting detailed issues for resolution. You will also ensure zero functional regression across product releases by executing comprehensive regression testing suites.

In addition, you will contribute to the creation and enhancement of detailed test plans for new product features and updates, collaborate closely with Development teams to support troubleshooting and effective root-cause analysis, and uphold Synopsys' high standards for product quality and long-term reliability through proactive quality initiatives.

As a member of our team, you will participate in code reviews and provide feedback on testability and quality improvements. You will deliver high-quality, reliable software that powers cutting-edge technologies in AI, 5G, and autonomous systems, ensuring seamless user experiences for our global customer base, including leading semiconductor and tech companies.

To succeed in this role, you will need a Bachelor's or Master's degree in Electronics Engineering / Semiconductor Engineering or a related field, with a minimum of 6 years of experience in industry or 5 years of industry experience with a Master's degree in a related field.

You will be proficient in scripting in shell, python, tcl, and have experience in EDA tools and AI systems. You will also be able to work in a fast-paced development cycle, autonomously and proactively manage quality and defect tracking, and have solid analytical and troubleshooting skills, especially in complex systems.

If you are a detail-oriented and analytical individual with a rigorous approach to problem-solving, a collaborative and communicative team player with strong written and verbal communication skills in English, we encourage you to apply for this exciting opportunity.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are a seasoned hardware engineering professional with a passion for advanced silicon package design and a proven track record in delivering innovative solutions for complex semiconductor challenges. With more than a decade of hands-on experience in package and interposer design, you possess a deep understanding of the latest advancements in 3DIC and multi-physics analysis.

Collaborating with cross-functional teams during early design stages to optimize and define SIPI (Signal Integrity/Power Integrity) performance requirements, including bump mapping and power estimation.

Designing and developing advanced silicon package solutions such as silicon interposers, RDL fanout packages, and silicon bridge packages.

Modeling and analyzing advanced package designs to ensure optimal electrical, thermal, and mechanical performance.

Representing Synopsys on business unit projects as a technical leader and subject matter expert in advanced packaging.

Resolving a wide range of design and integration issues using creative, data-driven approaches.

Supporting customer engagements in exploring and implementing advanced package solutions with Synopsys IPs.

Collaborating with global teams to share best practices and drive innovation in advanced packaging methodologies.

Empowering Synopsys and its customers to deliver next-generation, high-performance silicon solutions.

Accelerating the adoption of advanced packaging technologies that enable new levels of integration and energy efficiency.

Enhancing the performance, reliability, and manufacturability of Synopsys IP test chip packages.

Driving technical excellence and innovation in business unit projects that define Synopsys' leadership in the semiconductor industry.

Mentoring and guiding engineering peers, fostering a culture of knowledge sharing and continuous improvement.

Setting new industry standards for quality, performance, and innovation in advanced package design.

Building and strengthening customer relationships through expert support and collaboration.

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Key responsibilities include:

• Defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability.
• Driving the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.
• Mapping RTL designs into FPGA environments, utilizing deep verification and implementation knowledge to facilitate smooth prototyping and validation.
• Generating and packaging diagnostic tests for both production and field use, ensuring robust system performance and rapid troubleshooting.

As a Staff Hardware Engineer, you will work closely with cross-functional teams to accelerate the development of next-generation technologies through advanced FPGA design and integration. You will strengthen team productivity and knowledge by actively collaborating, mentoring, and sharing expertise with colleagues.

Requirements include:

• BS/MS in Computer Science, Electrical Engineering, or a related field.
• 5+ years of hands-on experience in RTL design and verification, preferably with complex FPGA systems.
• Proficiency in Hardware Description Languages such as VERILOG, VHDL, or SystemVerilog.
• Expertise in using industry-standard EDA tools and methodologies for design and verification.
• Hands-on experience with FPGA flows and tools like Vivado, and familiarity with Unix/Linux environments.
• Experience with scripting languages (Shell, Perl, Python, TCL) for automation and productivity enhancement.
• Background in HDL simulation, emulation, and prototyping platforms (e.g., Zebu, HAPS).
• Strong logical thinking and problem-solving abilities, with a keen attention to detail.

Benefits include:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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Key responsibilities include:

• Driving RTL-to-GDSII implementation for complex digital IP, ensuring signoff timing and PV closure.
• Leading backend flow development, including PnR, STA, DRC, LVS, and EMIR analysis.
• Collaborating with design, CAD, and cross-functional teams to optimize backend methodologies and resolve technical issues.
• Supporting project execution by troubleshooting timing, congestion, and physical verification challenges.

You will be part of the dynamic Design Support Group (DSG) at Synopsys, a passionate collective of engineers dedicated to delivering world-class backend solutions. Our team thrives on innovation, collaboration, and a shared commitment to technical excellence. We work closely with customers and internal teams, supporting them through every stage of their design journey and continually pushing the boundaries of what's possible in digital backend technology.

As a Staff Engineer, you will have the opportunity to work on cutting-edge projects, develop your technical skills, and contribute to the growth and success of the company. You will be part of a dynamic and supportive team that values innovation, collaboration, and technical excellence.

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You are a seasoned analog architect with deep expertise in high-speed interface design. You enjoy leading technical coordination, collaborating with diverse teams, and driving innovation. Your communication skills and mentoring abilities help foster a positive, inclusive engineering environment. You’re ready to make an impact on our advanced 224G and future 448G products.

Responsibilities: Coordinating engineering efforts for 224G and 448G analog products Architecting high-speed SerDes solutions Collaborating with cross-functional teams Mentoring junior engineers Defining design standards and methodologies Managing project timelines and resources Interfacing with customers and key external partners on SerDes technical topics

The Impact You Will Have: Enable launch of industry-leading analog products Drive technical excellence and innovation Mentor and develop engineering talent Set new benchmarks power, latency, area, and performance Shape Synopsys’ future in high-speed connectivity Accelerate adoption of advanced SerDes IP

What You’ll Need: Experience in high-speed analog IC design (224G/448G) Strong technical coordination skills Proficiency with EDA tools Solid understanding of circuit architecture and signal integrity Knowledge of semiconductor manufacturing processes

Who You Are: Innovative and collaborative leader Excellent communicator Detail-oriented and quality-focused Adaptable and eager to learn

The Team You’ll Be A Part Of: Join a multidisciplinary engineering team dedicated to developing high-speed analog IP for next-generation silicon platforms.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details during the hiring process.

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They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

Responsibilities

• Design, implement, and optimize compilation algorithms for mapping large-scale processor hardware descriptions onto the ZeBu emulator
• Develop scalable solutions to handle multi-billion-gate designs within tight runtime and memory constraints
• Apply advanced problem-solving skills to debug complex compilation, placement, and performance issues
• Develop and maintain high-quality, modular, and extensible object-oriented software in C++
• Collaborate closely with hardware architects, performance engineers, and emulator platform teams to ensure seamless integration and performance
• Contribute to continuous improvement of compilation flows, algorithms, and infrastructure for enhanced efficiency and robustness
• Participate in code reviews, design discussions, and knowledge sharing sessions with the broader engineering community

Impact

• Enable leading semiconductor companies to verify next-generation processor designs before commercialization
• Drive performance and scalability improvements, reducing compile and placement times for massive hardware designs
• Advance state-of-the-art compilation technologies in emulation, directly shaping the future of chip verification
• Enhance robustness and reliability of the ZeBu emulation platform, ensuring successful deployment in real-world scenarios
• Foster innovation and collaboration within the ZeBu Compiler Team and across Synopsys engineering groups
• Support industry leaders in achieving faster time-to-market for their products through efficient emulation workflows
• Champion best practices in software engineering, contributing to the overall quality and maintainability of the codebase

Requirements

• 3-5 years of relevant experience
• Strong skills in problem solving and algorithmic thinking, with proven experience in tackling challenging technical problems
• Solid expertise in object-oriented programming (preferably C++)
• Deep understanding of data structures and algorithms, with the ability to design efficient and scalable solutions
• Experience working with complex systems and large codebases
• Strong analytical skills and meticulous attention to detail
• Exposure to performance optimization, memory efficiency, or parallel computing (preferred)
• Familiarity with hardware description languages (Verilog, SystemVerilog, VHDL) (preferred)
• Experience with emulation, FPGA, EDA tools, or large-scale system software (preferred)

Team

You’ll join the ZeBu Compiler Team,a group of passionate engineers dedicated to advancing emulation technology for the world’s leading semiconductor companies. The team focuses on developing innovative compilation algorithms, scalable software solutions, and robust infrastructure to enable efficient verification of massive hardware designs. Collaboration, knowledge sharing, and a commitment to excellence define the team’s culture, empowering each member to make a meaningful impact.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Your expertise in high-speed, high-density board design enables you to tackle complex challenges, from 200G signaling to intricate HDI stack-ups. You are passionate about optimizing performance and reliability, and you possess a deep understanding of the full hardware development cycle—from schematic entry to final deliverables.

You are proficient with industry-standard EDA tools and comfortable managing libraries and constraints, ensuring accuracy and efficiency throughout the design process. Your strong communication skills enable you to share ideas, learn from others, and drive progress within a diverse team.

Design and optimize PCB layouts for cutting-edge HAPS hardware platforms, focusing on high-speed and high-density applications.

Collaborate with global teams to perform placement of small and large PCBAs, ensuring efficient use of space and signal integrity.

Execute complex routing tasks across multi-layer boards (from 8–16 layers up to 50+ layers), including blind and buried vias.

Work closely with colleagues on stack-up design and collaboration, contributing to robust and reliable board architectures.

Generate and manage PCB deliverables, including manufacturing files, BOMs, and assembly documentation.

Conduct DFx (Design for Excellence) checks, ensuring manufacturability, reliability, and compliance with industry standards.

Maintain and update EDA libraries, supporting rapid development and accurate component integration.

Participate in schematic entry, constraint management, and overall hardware design workflow.

Enable Synopsys to deliver industry-leading FPGA-based prototyping systems for semiconductor innovation.

Enhance product reliability and performance through meticulous PCB design and layout optimization.

Accelerate development cycles by collaborating across time zones and ensuring seamless deliverables.

Support high-speed signaling and connectivity, powering next-generation AI, automotive, and IoT solutions.

Drive improvements in manufacturability and quality, reducing costs and increasing customer satisfaction.

Contribute to the global success of HAPS hardware platforms, making a tangible difference in the tech industry.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are seeking an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology.

With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes.

You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus.

Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

You are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements.

As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment.

Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions.

You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.

Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.

Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.

Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.

Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.

Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses.

Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market.

Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps.

Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges.

Contribute to the development of next-generation verification methodologies and best practices within Synopsys.

Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.

5-8 years of hands-on experience in the Physical Verification (PV) domain.

Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.

Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.

Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.

Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.

Exposure to competitive EDA tools and awareness of their strengths and limitations.

An analytical thinker with strong problem-solving abilities and meticulous attention to detail.

A collaborative team player who fosters knowledge sharing and mentorship.

Effective communicator, capable of translating technical concepts to diverse audiences.

Adaptable and proactive, with a passion for continuous learning and innovation.

Customer-focused, with a commitment to delivering high-quality solutions on time.

Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

Join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design.

Work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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We are seeking a proactive, results-driven leader with a deep technical background in physical design and processor implementation. Your expertise is grounded in architecting high-performance, energy-efficient silicon solutions, and you thrive in fast-paced, collaborative environments. You possess a strong sense of ownership and are comfortable navigating ambiguity to deliver innovative solutions to complex engineering challenges.

As an Applications Engineering Architect (PPA), you will be responsible for architecting and executing the physical design of high-performance, energy-efficient processors and processor-based subsystems, targeting aggressive power and performance goals for diverse end-user applications. You will develop and refine advanced EDA tools and design methodologies to support state-of-the-art processor implementations.

Key Responsibilities:

• Architecting and executing the physical design of high-performance, energy-efficient processors and processor-based subsystems
• Developing and refining advanced EDA tools and design methodologies
• Collaborating closely with key Synopsys customers to guide their development of processor-based platforms in advanced silicon technologies
• Partnering with Synopsys R&D and marketing teams to influence and define future product roadmaps and features
• Working in synergy with leading IP partners to ensure seamless integration of EDA tools, methodologies, and IP

Requirements:

• Proven expertise in physical design and implementation of high-performance processors, SoCs, or processor-based subsystems
• In-depth experience with advanced EDA tools, flows, and methodologies for digital implementation
• Strong knowledge of silicon technologies at advanced nodes and associated design challenges
• Hands-on experience integrating IP and collaborating with IP vendors for seamless tool and methodology interoperability
• Track record of working directly with customers, understanding their requirements, and delivering tailored solutions

We offer a comprehensive range of health, wellness, and financial benefits, including medical, dental, and vision insurance, 401(k) matching, and paid time off. We also provide opportunities for professional growth and development, including training and education programs, mentorship, and career advancement opportunities.

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Your contributions will drive innovation in SRAM IP design, maintaining Synopsys’s leadership in memory technology. You will enhance product performance and reliability for global semiconductor customers. You will support the delivery of best-in-class SRAM compilers used in high-performance silicon chips. You will strengthen quality assurance processes, ensuring robust and scalable designs. You will accelerate time-to-market for new memory IP solutions through efficient verification and debug activities. You will contribute to the development of advanced memory architectures, impacting next-generation electronic devices.

To be successful in this role, you will need a Master’s degree in Electrical/Electronic Engineering or a related field. You will have 3–7+ years of hands-on experience in SRAM circuit design. You will have prior understanding of CMOS-based block level circuit design and SRAM architectures. You will have experience with SP/2P/ROM variety design and SRAM bitcell analysis. You will be proficient in digital circuit design and VLSI process concepts. You will have familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell. You will have experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR. Post-silicon debug experience is a plus.

You will be an analytical thinker with strong problem-solving skills. You will be curious and eager to learn new technologies and concepts. You will be detail-oriented and committed to delivering high-quality results. You will be a collaborative team player with effective communication skills. You will be adaptable and able to manage multiple tasks in a fast-paced environment. You will be self-motivated and resourceful in overcoming technical challenges.

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You are a driven and curious engineering professional, passionate about tackling complex technical challenges and eager to make a real difference in the semiconductor industry. You thrive in collaborative, diverse environments and are energized by working alongside global experts to solve high-value problems. You are committed to continuous learning and growth, staying ahead of the curve in verification methodologies, HDL/HVL technologies, and dynamic simulation.

Collaborate with customers to understand their verification challenges and provide tailored technical solutions using Synopsys Verification Platform. Support customer projects throughout their tapeout schedules, ensuring timely resolution of technical issues and successful project outcomes. Deliver technical presentations, workshops, and training sessions on Synopsys EDA tools, methodologies, and best practices.

Enable customers to optimize and verify chips for power, cost, and performance—accelerating their time-to-market. Build strong, collaborative relationships with customers, fostering trust and loyalty through expert support and innovation. Drive adoption of Synopsys Verification Platform, contributing to company growth and industry leadership.

Master’s degree in Electronics, or Bachelor’s degree in Electronics with 1-2 years of relevant experience. Solid understanding of digital design, HDLs (Verilog, VHDL), and System Verilog. Experience with dynamic simulation verification, including methodologies, debug, low power, and coverage. Familiarity with Synopsys EDA tools (VCS, Verdi) is a plus. Proficiency in UNIX environments and scripting languages such as Tcl, with the ability to automate and optimize workflows.

Collaborative team player who values diversity and inclusion. Detail-oriented, organized, and able to manage multiple priorities effectively. Innovative thinker with a proactive, results-driven mindset. Motivated, self-organized, and open to travel as required. Strong interpersonal and social communication skills, fostering positive relationships with colleagues and clients. Adaptable and eager to learn, embracing new technologies and methodologies.

You’ll be part of the Customer Success Group, a collaborative and diverse team dedicated to building strong partnerships with market leaders and innovators. The team’s core mission is to enable customers to solve high-value problems through advanced verification solutions and continuous technical support. Working closely with domain experts across global locations, you’ll develop deep expertise in Synopsys Verification Platform and play a key role in helping customers achieve their design goals efficiently and effectively.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We are seeking an experienced AI/GenAI engineer to join our team at Synopsys. As a Principal AI/GenAI Engineer, you will design, develop, and deploy GenAI Agentic and machine learning models, algorithms, and systems to tackle complex business challenges.

What You'll Be Doing:

• Design, develop, and deploy GenAI Agentic and machine learning models, algorithms, and systems to tackle complex business challenges.
• Provide technical leadership and mentorship, supporting junior engineers and data scientists in best practices and advanced techniques.
• Stay abreast of the latest AI, Agentic AI, and machine learning advancements, applying them to enhance existing systems or develop innovative solutions.
• Collaborate with program and product managers, software engineers, and stakeholders to define requirements and create technical specifications for AI solutions.
• Conduct data analysis, preprocessing, and feature engineering to prepare datasets for machine learning models.
• Train, validate, and fine-tune machine learning models to meet performance and accuracy benchmarks.
• Deploy AI models into production environments, monitoring and optimizing their performance.
• Document models, algorithms, and methodologies to ensure reproducibility and facilitate knowledge sharing.
• Ensure all AI solutions comply with ethical guidelines, data privacy regulations, and industry standards.

The Impact You Will Have:

• Accelerate innovation in AI-driven products and solutions, directly influencing Synopsys' technological leadership.
• Enhance operational efficiency and decision-making through intelligent automation and data-driven insights.
• Drive adoption of Agentic AI systems, enabling transformative business outcomes across multiple domains.
• Mentor and elevate the technical capabilities of the engineering and data science teams, fostering a culture of excellence.
• Champion ethical AI practices, ensuring responsible development and deployment of cutting-edge technologies.
• Support cross-functional collaboration, bridging the gap between technical and business teams for successful project delivery.
• Contribute to the advancement of semiconductor IPs and EDA tool integration with AI, expanding Synopsys' product portfolio.

What You'll Need:

• Ph.D. or Master’s degree in Computer Science, Data Science, Electrical Engineering, or a related field.
• Minimum 8 years of experience in software engineering, machine learning, and GenAI, with a proven track record in production deployments.
• Strong proficiency in Python; familiarity with backend and distributed systems, message queues, and orchestration technologies is a plus.
• Expertise in data structures, algorithms, and design patterns for scalable AI solutions.
• Extensive experience with machine learning and Agentic frameworks (e.g., TensorFlow, PyTorch, LangChain/LangGraph, AutoGen) and LLM models.
• Strong grasp of statistical analysis, data mining, and data visualization techniques.
• Knowledge of cloud platforms, containerization (Kubernetes, Docker), and version control systems (Git, P4).
• Familiarity with Agile, Kanban, or Scrum methodologies.
• Understanding or experience with semiconductor IPs and EDA tools is highly desirable.

Who You Are:

• Exceptional problem-solving and analytical abilities, with a strategic mindset.
• Strong communication and interpersonal skills to engage diverse audiences.
• Ability to work independently and collaboratively within multidisciplinary teams.
• Demonstrated leadership and mentorship capabilities.
• Adaptable, proactive, and eager to continuously learn and innovate.

The Team You’ll Be A Part Of:

You will join a dynamic, collaborative group of professionals dedicated to advancing AI and GenAI solutions for diverse projects. The team values innovation, knowledge sharing, and continuous improvement, working closely with product managers, engineers, and stakeholders to deliver impactful AI-powered systems. You will play a key role in mentoring, technical leadership, and driving the evolution of Synopsys’ AI initiatives.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You enjoy solving complex problems and are not afraid to explore new methods and technologies. You bring a strong analytical mindset, excellent problem-solving skills, and a willingness to learn from both successes and setbacks. You value diversity and inclusion, recognizing that the best solutions come from teams with varied perspectives. You take pride in your work, communicate effectively, and are motivated to deliver high-quality results. Whether you are fresh out of graduate school or have a few years of hands-on experience, you are ready to take on new challenges and contribute to innovations that power the next generation of intelligent devices.

What You’ll Be Doing:

• Designing and verifying the robustness of SRAM integrated circuits, ensuring optimal performance and reliability.
• Developing and enhancing SRAM compilers, including GDS and netlist tiling for efficient memory layout and integration.
• Characterizing SRAM modules for timing, power, and functional parameters to meet stringent specifications.
• Analyzing and developing SRAM bitcell design criteria, supporting a wide range of memory architectures.
• Utilizing EDA tools (XA, Hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization.
• Collaborating with cross-functional teams to resolve post-silicon issues and continuously improve memory IP quality.
• Exploring new SRAM architectures including SP, 2P, and ROM varieties, contributing to innovation in IP solutions.

The Impact You Will Have:

• Advance the capabilities of Synopsys’s SRAM IP, strengthening its position as an industry leader.
• Deliver high-performance, reliable memory solutions that enable next-generation chips for global customers.
• Drive innovation by creating robust, scalable, and energy-efficient SRAM designs.
• Enhance the efficiency and productivity of the design team through automation and process improvements.
• Support successful silicon tapeouts and post-silicon validation, ensuring product excellence.
• Contribute to a collaborative and inclusive team culture that values knowledge sharing and continuous learning.

What You’ll Need:

• Master’s degree in Electrical/Electronic Engineering or a related field.
• Strong understanding of CMOS-based block level circuit design and SRAM architectures.
• Solid grasp of digital circuit design and VLSI process concepts.
• Familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell for workflow automation.
• Experience 3~10 years in SRAM circuit design, bitcell analysis, and design criteria development.
• Knowledge of SP/2P/ROM variety designs and post-silicon debug processes is a plus.
• Proficiency with EDA tools including XA, Hspice, Verilog, Starrc, and EMIR for simulation and verification.

Who You Are:

• Innovative thinker with a strong desire to learn and explore new technologies.
• Detail-oriented and analytical, capable of tackling complex technical challenges.
• Collaborative team player who values diverse perspectives and open communication.
• Effective communicator able to present ideas clearly and work across global teams.
• Resilient and adaptable, able to thrive in a fast-paced, ever-evolving environment.
• Proactive problem solver who takes ownership of projects and drives results.

The Team You’ll Be A Part Of:

You will join Synopsys’s world-class SRAM circuit and compiler design department, the largest of its kind globally. Our team is at the forefront of memory IP solutions, working collaboratively to deliver robust, high-performance SRAM products for a diverse range of applications. We foster a culture of innovation, knowledge sharing, and continuous improvement, empowering each member to contribute to the advancement of cutting-edge technologies in semiconductor design.

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What You'll Be Doing:

• Develop accurate timing models for macros used in multi-die designs.
• Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements.
• Collaborate closely with IP design teams to maintain high-quality timing arcs and adhere to timing methodology standards.
• Assist in timing analysis and closure for high-speed interfaces and mixed-signal IP blocks.
• Perform STA (Static Timing Analysis) using industry-standard EDA tools.
• Support constraint development and validation for timing sign-off.
• Collaborate with design, verification, and physical implementation teams to resolve timing issues.
• Utilize SiliconSmart for SPICE-based characterization and NanoTime for transistor-level Static Timing Analysis (STA)

Authority:

• Normally receives detailed instructions on all work.
• Follows standard practices and procedures in analyzing situations or data from which answers can be readily obtained.
• Applies company policies and procedures to resolve routine issues.

What You'll Need:

• Bachelor's or Master's degree in Electronics - Electrical Engineering, or Telecommunications; Computer Science Engineering or related ones.
• 1-2 year working experience in similar roles or fresh graduates

(Fresh graduates are also welcomed and offered the on-the-job training to adapt the position's requirements.)

• Basic understanding of timing analysis, SPICE simulation, and STA concepts.
• Experience with scripting languages such as Python and TCL for automation and data processing.
• Familiarity with EDA tools for timing characterization and verification.
• Strong problem-solving abilities and keen attention to detail.
• Good verbal and written English communication skills.
• Highly responsible and self-motivated, with a strong sense of ownership over your work.
• Collaborative team player, open to feedback and eager to learn from others.
• Detail-oriented and methodical, always striving for accuracy and quality.
• Effective communicator, able to articulate technical concepts clearly.
• Adaptable and resilient in the face of new challenges or shifting priorities.
• Enthusiastic about contributing to a diverse, inclusive, and innovative workplace.

The Team You’ll Be A Part Of:

You’ll join the Synopsys UCIe Design Team, a dynamic group of engineers specializing in advanced chiplet interconnect and analog mixed-signal technologies. This is global team, which is working on state-of-the-art UCIe, 2.5D/3D IC, and Tbps die-to-die interfaces.

As a team member, you’ll receive structured training, mentorship, and exposure to the complete design flow, helping you grow into a technical expert or future design leader. If you are passionate about precision timing analysis and eager to work in a collaborative, innovative environment, we’d love to have you on our team.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What is it like to be an Analog Design Engineer at Synopsys?

Arman Shahmuradyan

Analog Design, Manager

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

16005

Remote Eligible

No

Date Posted

03/05/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished and forward-thinking engineering professional with a deep passion for the intersection of artificial intelligence and semiconductor design. Your expertise spans RTL-to-GDSII flows, and you have hands-on experience with industry-leading EDA tools, especially those driving the next generation of AI and high-performance compute silicon. You are highly analytical, able to dissect complex design challenges and architect robust, scalable solutions that address both immediate and future technology needs. You thrive in customer-facing roles, translating requirements into actionable methodologies and championing innovation every step of the way.

What You’ll Be Doing:

• Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.

• Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.

• Enabling and deploying flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, utilizing Tcl/Python scripting for automation.

• Collaborating cross-functionally with customers, R&D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges.

• Leading and mentoring a team of junior application engineers, providing technical guidance, coaching, and project management support to ensure successful execution of deliverables.

• Delivering technical presentations, application notes, and best practices to both internal and external stakeholders, supporting knowledge-sharing and customer enablement.

The Impact You Will Have:

• Accelerate customer adoption of next-generation AI-driven design methodologies, empowering them to achieve breakthrough silicon results.

• Shape Synopsys’ technology direction by providing valuable field insights and partnering with R&D on new feature development.

• Reduce time-to-market and improve competitiveness for customers through innovative flow optimization and automation.

• Drive Synopsys’ leadership in AI-powered EDA solutions, further differentiating our offerings in a competitive market.

• Elevate the technical capabilities of the application engineering team through mentorship and cross-training.

• Enhance customer satisfaction and loyalty through proactive engagement, expert troubleshooting, and tailored technical support.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5 + years of relevant experience.

• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).

• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes.

• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.

• Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.

• Outstanding verbal and written communication, presentation, and customer interaction skills.

Who You Are:

• Collaborative and empathetic leader, skilled at building relationships and enabling the success of others.

• Analytical thinker with a problem-solving mindset and a passion for continuous improvement.

• Adaptable and resilient in the face of evolving customer requirements and technology landscapes.

• Strong organizational skills, able to manage multiple projects and priorities with poise.

• Driven by curiosity and a desire to innovate at the forefront of AI and semiconductor design.

The Team You’ll Be A Part Of:

You’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. With a culture rooted in collaboration, technical excellence, and mentorship, you’ll have the opportunity to lead, learn, and contribute to the next wave of EDA innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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You are a passionate and versatile engineering professional who thrives in a dynamic, fast-paced environment. With a deep technical acumen and a knack for creative problem-solving, you are driven to deliver innovative solutions that address complex challenges. You have a proven track record in application engineering, accompanied by a strong understanding of EDA tools, chip design flows, and customer-centric solution delivery.

Responsibilities

• Collaborating with customers to understand their technical challenges and providing comprehensive solutions using Synopsys tools and platforms.
• Driving the adoption and integration of EDA tools in customer design flows, ensuring optimal utilization and performance.
• Developing and delivering technical workshops, training sessions, and product demonstrations tailored to customer needs.
• Partnering with R&D and product management teams to influence product direction and resolve complex technical issues.
• Authoring and maintaining technical documentation, application notes, and best practice guides.
• Providing pre- and post-sales technical support, including troubleshooting, bug tracking, and solution development.
• Mentoring and guiding junior engineers, fostering a culture of technical excellence and innovation.

Impact

• Accelerating customer success by ensuring seamless deployment and integration of Synopsys solutions.
• Enhancing product quality and usability through direct feedback and collaboration with R&D teams.
• Expanding Synopsys' footprint in key accounts by demonstrating technical excellence and building strong customer relationships.
• Reducing design cycle times and improving overall productivity for our customers.
• Contributing to the growth of Synopsys' technical community through knowledge sharing and mentoring.
• Influencing future product innovations by identifying emerging customer needs and market trends.

Requirements

• Strong expertise in ASIC/FPGA design and verification methodologies.
• Hands-on experience with industry-leading EDA tools such as synthesis, simulation, and formal verification platforms.
• Proficiency in scripting languages (e.g., Python, Perl, TCL) and automation frameworks.
• Solid understanding of digital design, SoC architectures, and semiconductor manufacturing processes.
• Ability to analyze and resolve complex technical issues quickly and effectively.

Team

You'll join an accomplished team of application engineering experts at the forefront of EDA and semiconductor innovation. Our team partners closely with customers, R&D, and product management to deliver world-class solutions and technical support. We foster a collaborative, inclusive culture that encourages continuous learning, knowledge sharing, and professional growth.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are: You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

Responsibilities: Develop and validate DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies. Collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python. Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions. Mentor junior team members, share best practices, and contribute to a knowledge-sharing culture within the team. Stay up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

Impact: Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. Contribute to the development of next-generation verification methodologies and best practices within Synopsys. Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

Requirements: B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field. 5-8 years of hands-on experience in the Physical Verification (PV) domain. Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS. Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development. Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements. Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks. Exposure to competitive EDA tools and awareness of their strengths and limitations.

Who You Are: An analytical thinker with strong problem-solving abilities and meticulous attention to detail. A collaborative team player who fosters knowledge sharing and mentorship. Effective communicator, capable of translating technical concepts to diverse audiences. Adaptable and proactive, with a passion for continuous learning and innovation. Customer-focused, with a commitment to delivering high-quality solutions on time. Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

The Team You’ll Be A Part Of: You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

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Collaborate to define product goals Conceive, design, evaluate, and produce novel gaming hardware Work closely with contract manufacturers to prototype and produce hardware at scales from tens to millions of units

Electrical engineers at Valve have significant industry experience. We usually don’t hire recent graduates.

Members of our team typically have the following skills:

Proven start-to-finish design skills with industry-standard CAD/EDA tools (Altium Designer experience strongly preferred), including schematic entry, PCB layout, component definition, and CAD library management Hands-on electronics prototyping experience, including soldering and rework of fine-pitch SMT components Strong lab skills, including the use of common test and measurement equipment (oscilloscopes, logic analyzers, etc.) to debug and characterize complex electronic circuits Experience with embedded systems design and common digital communication interfaces (USB, SPI, I2C) Experience working directly on-site with manufacturing partners A proven track record of designing and shipping high-volume consumer electronics products Experience in design for manufacture and design for test (DFM/DFT) of electronic devices Ability to think and work across a variety of subject areas

Bachelor's degree (or equivalent work experience) in electrical engineering or a related field

Our team includes individuals with expertise in the following areas:

Analog circuit design and simulation (e.g. SPICE) Low-power design, including battery management and charging circuits for portable devices RF/wireless circuit design, including design of antennas and for EMC Firmware development for 8, 16, 32-bit microcontrollers (e.g. ARM) High speed/HDI board design Digital Signal Processing (DSP) High speed video interfaces (HDMI, Display Port, LVDS, MIPI) Regulatory compliance testing (e.g. FCC/CE/UL) C/C++ software development Test automation FPGA/ASIC design

What We Offer

An organization where 100% of time is dedicated as groups see fit The opportunity to collaborate with experts across a range of disciplines A work environment and flexible schedule in support of families and domestic partnerships A culture eager to become stronger through diversity of all forms Exceptional health insurance coverage Unrivaled employer match for our 401(k) retirement plan Generous vacation and family leave On-site amenities in support of health and efficiency Fertility and adoption assistance Reimbursement for child care during interviews

Valve strives to improve the diversity of our teams to better serve our diverse global audience. We welcome and encourage individuals from all backgrounds to apply.

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What you'll do

• Providing world-class support to customers and channel partners, ensuring effective usage and satisfaction with Apache BU simulation products focused on Power, Power Integrity, and Reliability.
• Applying advanced knowledge in custom circuit analysis, RTL design, high-performance VLSI design, standard cell physical layout, power-grid extraction, timing analysis, noise analysis, and voltage drop effects to solve complex SoC challenges.

What you need

• Bachelor’s degree in Electrical Engineering (BSEE) with at least 6 years of experience, Master’s degree (MSEE) with 4 years, or PhD with 2 years in VLSI design.
• Expertise in custom circuit analysis, standard cell physical layout, timing and noise analysis, and voltage drop effects using CAD tools.
• Strong technical knowledge of EDA tools for layout, STA, Extraction (SPEF/DSPF), and Spice simulation.

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What you'll do

• Provide expert support and training to customers on Totem and related Semiconductor Business Unit simulation products, ensuring high productivity and satisfaction.
• Independently coordinate and manage support for multiple customer designs through tape-out, verifying design quality and compliance with expectations.
• Apply advanced knowledge in analog circuit analysis, VLSI design, power-grid extraction, noise analysis, and ESD to solve complex SoC challenges.

What you need

• Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE) with at least 3 years of relevant experience.
• Advanced expertise in custom circuit analysis & design, physical layout, noise analysis, voltage drop effects, and ESD using CAD tools.
• Strong technical knowledge of EDA tools, especially for layout and analog circuit extraction (SPEF/DSPF).
• Proficiency in UNIX operating systems and scripting languages such as Perl, Tcl, or Python for troubleshooting and utility development.
• Excellent verbal and written communication skills in both English and Mandarin, with the ability to convey complex concepts clearly.

XML job scraping automation by YubHub

What you'll do

• Designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.
• Developing comprehensive test cases to ensure robust product functionality and performance.

What you need

• BS/MS in Computer Science, Electrical Engineering, or related field.
• 5 years of hands-on experience in RTL design and verification.

XML job scraping automation by YubHub

What you'll do

• Define and implement UCIe PHY for automotive applications.
• Design and verify digital IP and ASIC solutions.
• Create and review FMEDA, DFMEA, and DFA work products for UCIe PHY.
• Apply ISO 26262 functional safety standards.
• Collaborate with cross-functional teams and support validation.

What you need

• Experience in digital IP/ASIC design for automotive.
• UCIe PHY and SoC architecture knowledge.
• Familiarity with ISO 26262, FMEDA, DFMEA, DFA.
• Proficiency with EDA tools.

XML job scraping automation by YubHub

What you'll do

• Design and develop high-speed analog and mixed-signal ICs
• Collaborate with cross-functional teams to develop and implement new design methodologies and tools

What you need

• Bachelor's degree in Electrical Engineering or related field
• 3+ years of experience in analog and mixed-signal IC design
• Strong understanding of analog and mixed-signal circuit design and analysis
• Experience with SPICE simulators and EDA tools
• Strong communication and teamwork skills

XML job scraping automation by YubHub

What you'll do

• Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment.
• Collaborate with cross-functional teams to ensure successful project execution.
• Create and review layout documents to ensure they meet quality standards and are delivered on time.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Minimum 3+ years of experience in Analog and Mixed Signal Circuit Layout.

XML job scraping automation by YubHub

What you'll do

• Guiding customers through the integration of Synopsys UCIe IP into their ASIC SoC and systems, addressing both technical and process challenges.
• Providing expert advice on IIP configuration, simulation, synthesis, floorplanning, static timing analysis (STA), and design-for-test (DFT) strategies.

What you need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Minimum 10 years of experience in ASIC design, verification, or applications engineering within advanced technology nodes (10nm/7nm/5nm/3nm).
• Hands-on expertise in mixed-signal and high-speed interface design and integration, ASIC front-end and/or back-end implementation, including simulation, synthesis, floorplanning, and DFT.

XML job scraping automation by YubHub

What you'll do

• Developing and implementing SOC design using Synopsys EDA tools and IP, covering all stages from spec to post-silicon bring-up.
• Contributing to both turnkey projects and serving as a trusted advisor to customer design and CAD teams.

What you need

• BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.
• 4 to 7+ years of hands-on experience in Place & Route domains using Fusion Compiler/ICC2 tool.

XML job scraping automation by YubHub

What you'll do

• Leading the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.
• Collaborating closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.

What you need

• Extensive experience in ASIC digital design and verification, with a strong background in RTL design.
• Proficiency in using industry-standard EDA tools and methodologies for design and verification.

XML job scraping automation by YubHub

What you'll do

• Leading the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.
• Collaborating closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.

What you need

• Extensive experience in ASIC digital design and verification, with a strong background in RTL design.
• Proficiency in using industry-standard EDA tools and methodologies for design and verification.

XML job scraping automation by YubHub

What you'll do

• Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.
• Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 9+ years of relevant experience.
• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).
• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes (like 2nm/3nm/5nm etc).
• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.
• Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.
• Outstanding verbal and written communication, presentation, and customer interaction skills.

XML job scraping automation by YubHub

What you'll do

• Developing and implementing SOC design using Synopsys EDA tools and IP, covering all stages from spec to post-silicon bring-up.
• Contributing to both turnkey projects and serving as a trusted advisor to customer design and CAD teams.

What you need

• BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.
• 7 to 10+ years of hands-on experience in Place & Route domains using Fusion Compiler/ICC2 tool.

XML job scraping automation by YubHub

What you'll do

As a Sr Staff SoC Engineer(Backend), you will be working as a member of the customer's IC design team, leveraging their experience and Synopsys' best practices to have immediate impact on their current project while transferring valuable knowledge for future projects.

• Assist customers in successfully tape out from Netlist to GDS by using Synopsys EDA tools
• Focus on design planning, floorplanning, place and route, parasitic extraction, signal integrity analysis and prevention, IR drop/EM analysis and physical verification (DRC/LVS)

What you need

• Typically requires BSEE or higher with 5+ years in physical design implementation role
• Familiar with Floorplan, Place and route, DRC/LVS, IR drop, EM and Signal Integrity etc.
• Familiar with STA, Formal Verification and Synthesis is better

XML job scraping automation by YubHub

What you'll do

• Designing and implementing custom analog layout for high-speed SERDES blocks, including TX, RX, and PLLs, in advanced technology nodes.
• Developing floor plans, optimizing power distribution networks, and executing signal routing strategies with a focus on EMIR, parasitic minimization, and yield improvement.

What you need

• 5+ years of hands-on experience in custom analog layout, with a focus on High-Speed SERDES (TX/RX/PLL) in deep submicron technologies.
• Proficiency in floor planning, power grid design, signal routing, and parasitic optimization.
• Expertise in industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor Calibre, Synopsys IC Compiler).
• Strong understanding of EMIR, DRC, LVS, ERC, ANT, ESD, DFM, and PERC verification methodologies.

XML job scraping automation by YubHub

What you'll do

• Collaborating with R&D teams to drive product development and advanced HPC reference flow development for wide deployment.
• Demonstrating differentiated PPA results on CPU/GPU/NPU designs to showcase our technology's superiority.

What you need

• BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience.
• Hands-on experience with synthesis and place and route (P&R) tools.

XML job scraping automation by YubHub

What you'll do

• Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
• Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.

What you need

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.
• 5-8 years of hands-on experience in the Physical Verification (PV) domain.
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
• Exposure to competitive EDA tools and awareness of their strengths and limitations.

XML job scraping automation by YubHub

What you'll do

• Developing and executing strategic account plans to drive revenue growth and achieve sales targets.
• Building and maintaining strong relationships with key decision-makers at enterprise clients.

What you need

• Extensive experience in enterprise sales within the semiconductor or technology industry.

XML job scraping automation by YubHub

What you'll do

• Understanding and documenting project scope, requirements, and deliverable dependencies across multiple cross-functional teams.
• Leading regular and ad hoc sync-up meetings with internal teams and customers to align goals, clarify requirements, and drive progress.

What you need

• MSEE/BSEE or MSCE/BSCE with 15+ years' experience in ASIC design and project management.
• Deep understanding of ASIC design flow (RTL to physical implementation) and familiarity with advanced EDA tools (e.g., Synopsys EDA tools).

XML job scraping automation by YubHub

What you'll do

You will be designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.

• Designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.
• Developing comprehensive test cases to ensure robust product functionality and performance.
• Collaborating with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis.
• Staying current with emerging trends, standards, and best practices in SLM and 3D-IC technologies.
• Contributing to the improvement of verification methodologies and automation flows.
• Documenting design specifications, verification plans, and results to ensure transparency and repeatability.
• Participating in code reviews and technical discussions to drive innovation and continuous improvement.

What you need

• BS/MS in Computer Science, Electrical Engineering, or related field.
• 8+ years of hands-on experience in RTL design and verification.
• Proficiency in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies.
• Experience working in Unix/Linux environments.
• Strong debugging and problem-solving skills, especially in complex chip design environments.
• Excellent written and verbal communication skills in English.
• Knowledge of digital, analog, and mixed-signal IP/circuit design (a plus).
• Familiarity with 3D-IC standards and semiconductor verification best practices (desirable).

XML job scraping automation by YubHub

What you'll do

Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment.

• Collaborate with cross-functional teams to ensure successful project execution.

• Create and review layout documents to ensure they meet quality standards and are delivered on time.

What you need

Bachelor's or Master's degree in Electrical Engineering or a related field.

• Minimum 9+ years of experience in Analog and Mixed Signal Circuit Layout.

XML job scraping automation by YubHub

What you'll do

Reviewing SERDES standards to develop innovative transceiver architectures and sub-block specifications for Multi-Gbps NRZ & PAM4 SERDES IP.

• Investigating and architecting advanced circuit solutions to overcome bottlenecks, achieving breakthroughs in power efficiency, area reduction, and performance.

What you need

• Collaborating with cross-functional teams including analog, digital, and layout engineers.

Why this matters

As a trusted leader in the analog design community, your attention to detail, ownership mindset, and commitment to quality position you for success.

XML job scraping automation by YubHub

What you'll do

Working on Functional Verification and Design Implementation.

• Using tools such as Formality, Formality-ECO, Fusion Compiler, or other EDA tools.

• Leveraging your understanding of advanced process nodes.

• Utilizing your scripting skills to automate processes.

What you need

BS with 3-5 years of direct hands-on experience.

• Proficiency in design closure.

• Experience with tools such as Formality, Formality-ECO, Fusion Compiler, or other EDA tools will be added value.

• Knowledge of Python, Perl, and TCL scripting languages.

XML job scraping automation by YubHub

What you'll do

Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.

• Demonstrating the unique advantages and capabilities of Synopsys' industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.

What you need

Bachelor's and/or Master's degree in Electrical Engineering or a related field.

XML job scraping automation by YubHub