{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/eda-tools-and-methodologies"},"x-facet":{"type":"skill","slug":"eda-tools-and-methodologies","display":"Eda Tools And Methodologies","count":4},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6d8de738-1a7"},"title":"Staff Hardware Engineer","description":"<p>We are seeking a skilled Staff Hardware Engineer to join our team in Cairo. As a Staff Hardware Engineer, you will be responsible for defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development. You will develop and optimize RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability. You will also drive the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development.</li>\n<li>Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability.</li>\n<li>Driving the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.</li>\n<li>Mapping RTL designs into FPGA environments, utilizing deep verification and implementation knowledge to facilitate smooth prototyping and validation.</li>\n<li>Generating and packaging diagnostic tests for both production and field use, ensuring robust system performance and rapid troubleshooting.</li>\n</ul>\n<p>As a Staff Hardware Engineer, you will work closely with cross-functional teams to accelerate the development of next-generation technologies through advanced FPGA design and integration. You will strengthen team productivity and knowledge by actively collaborating, mentoring, and sharing expertise with colleagues.</p>\n<p>Requirements include:</p>\n<ul>\n<li>BS/MS in Computer Science, Electrical Engineering, or a related field.</li>\n<li>5+ years of hands-on experience in RTL design and verification, preferably with complex FPGA systems.</li>\n<li>Proficiency in Hardware Description Languages such as VERILOG, VHDL, or SystemVerilog.</li>\n<li>Expertise in using industry-standard EDA tools and methodologies for design and verification.</li>\n<li>Hands-on experience with FPGA flows and tools like Vivado, and familiarity with Unix/Linux environments.</li>\n<li>Experience with scripting languages (Shell, Perl, Python, TCL) for automation and productivity enhancement.</li>\n<li>Background in HDL simulation, emulation, and prototyping platforms (e.g., Zebu, HAPS).</li>\n<li>Strong logical thinking and problem-solving abilities, with a keen attention to detail.</li>\n</ul>\n<p>Benefits include:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_6d8de738-1a7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/cairo/staff-hardware-engineer/44408/93286401152","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design and verification","Xilinx UltraScale, UltraScale+, and Versal FPGAs","Hardware Description Languages (VERILOG, VHDL, SystemVerilog)","Industry-standard EDA tools and methodologies","FPGA flows and tools (Vivado)","Unix/Linux environments","Scripting languages (Shell, Perl, Python, TCL)","HDL simulation, emulation, and prototyping platforms (Zebu, HAPS)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:19:26.758Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Cairo"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, Xilinx UltraScale, UltraScale+, and Versal FPGAs, Hardware Description Languages (VERILOG, VHDL, SystemVerilog), Industry-standard EDA tools and methodologies, FPGA flows and tools (Vivado), Unix/Linux environments, Scripting languages (Shell, Perl, Python, TCL), HDL simulation, emulation, and prototyping platforms (Zebu, HAPS)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f86d4f64-6b2"},"title":"UCIe Applications Engineer, Sr Staff","description":"<p>We are seeking a seasoned engineering professional with a deep passion for advancing semiconductor technology. As a UCIe Applications Engineer, Sr Staff, you will be responsible for guiding customers through the integration of Synopsys UCIe IP into their ASIC SoC and systems, addressing both technical and process challenges.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Guiding customers through the integration of Synopsys UCIe IP into their ASIC SoC and systems, addressing both technical and process challenges.</li>\n<li>Providing expert advice on IIP configuration, simulation, synthesis, floorplanning, static timing analysis (STA), and design-for-test (DFT) strategies.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.</li>\n<li>Minimum 10 years of experience in ASIC design, verification, or applications engineering within advanced technology nodes (10nm/7nm/5nm/3nm).</li>\n<li>Hands-on expertise in mixed-signal and high-speed interface design and integration, ASIC front-end and/or back-end implementation, including simulation, synthesis, floorplanning, and DFT.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f86d4f64-6b2","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/ucie-applications-engineer-sr-staff/44408/90867636768","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["ASIC design","verification","applications engineering","mixed-signal and high-speed interface design and integration","ASIC front-end and/or back-end implementation"],"x-skills-preferred":["EDA tools and methodologies","P&R","Physical Verification","Signal/Power Integrity"],"datePosted":"2026-03-06T07:24:14.000Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu, Taiwan"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC design, verification, applications engineering, mixed-signal and high-speed interface design and integration, ASIC front-end and/or back-end implementation, EDA tools and methodologies, P&R, Physical Verification, Signal/Power Integrity"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c160f208-ea8"},"title":"Principal Engineer, ASIC Digital Design","description":"<p>We are seeking a Principal Engineer, ASIC Digital Design to join our team in Munich, Germany. As a Principal Engineer, you will be responsible for leading the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Leading the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.</li>\n<li>Collaborating closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Extensive experience in ASIC digital design and verification, with a strong background in RTL design.</li>\n<li>Proficiency in using industry-standard EDA tools and methodologies for design and verification.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c160f208-ea8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/munich/principal-engineer-asic-digital-design/44408/91458064640","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["ASIC digital design and verification","RTL design","EDA tools and methodologies"],"x-skills-preferred":["High-Performance Interface IP protocols","Complex design challenges"],"datePosted":"2026-03-06T07:23:00.546Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Munich, Bavaria, Germany"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC digital design and verification, RTL design, EDA tools and methodologies, High-Performance Interface IP protocols, Complex design challenges"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_0a64aeaf-c20"},"title":"ASIC Digital Design, Architect","description":"<p>We are seeking an experienced ASIC Digital Design Engineer to join our team in Dublin. The successful candidate will be responsible for designing and verifying complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Leading the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.</li>\n<li>Collaborating closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Extensive experience in ASIC digital design and verification, with a strong background in RTL design.</li>\n<li>Proficiency in using industry-standard EDA tools and methodologies for design and verification.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_0a64aeaf-c20","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/dublin/asic-digital-design-architect/44408/91458064848","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC digital design and verification","RTL design","EDA tools and methodologies"],"x-skills-preferred":["High-Performance Interface IP protocols","Complex design challenges"],"datePosted":"2026-03-06T07:22:54.753Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Dublin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC digital design and verification, RTL design, EDA tools and methodologies, High-Performance Interface IP protocols, Complex design challenges"}]}