{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/dsi"},"x-facet":{"type":"skill","slug":"dsi","display":"Dsi","count":14},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_bb1df1a6-5fe"},"title":"CAE MODSIM Principal Engineer","description":"<p>What Makes a Honda, is Who makes a Honda</p>\n<p>Honda has a clear vision for the future, and it’s a joyful one. We are looking for individuals with the skills, courage, persistence, and dreams that will help us reach our future-focused goals. At our core is innovation. Honda is constantly innovating and developing solutions to drive our business with record success. We strive to be a company that serves as a source of “power” that supports people around the world who are trying to do things based on their own initiative and that helps people expand their own potential. To this end, Honda strives to realize “the joy and freedom of mobility” by developing new technologies and an innovative approach to achieve a “zero environmental footprint.”</p>\n<p>We are looking for qualified individuals with diverse backgrounds, experiences, continuous improvement values, and a strong work ethic to join our team.</p>\n<p>If your goals and values align with Honda’s, we want you to join our team to Bring the Future!</p>\n<p><strong>Job Purpose:</strong></p>\n<p>As a Principal CAE Engineer in the Advanced CAE Department, you will be responsible to lead a project or team for CAE model and method creation related to structural based CAE for strength and reliability. Proficient use and understanding of CAE methods contributes to improved optimization, speed, and efficiency of our products and development processes.</p>\n<p><strong>Key Accountabilities:</strong></p>\n<ul>\n<li>Lead and provide technical guidance for a team(s) or project(s) to develop and validate new CAE methods for both specification setting and product verification.</li>\n<li>Develops and evaluates metrics for quality of modeling and analysis.</li>\n<li>Assist in setting the plan for the technical direction of CAE methods development</li>\n<li>Collaborate with principal test and principal design engineers to ensure CAE models are achieving accuracy targets.</li>\n<li>Collaborate with other principal engineers to ensure the CAE methods are meeting the requirements for application to development projects.</li>\n<li>Create documentation for the registration of CAE Models as a verified tool for specification setting and product verification.</li>\n</ul>\n<p><strong>Qualifications, Experience, and Skills:</strong></p>\n<ul>\n<li>BS in mechanical engineering. Advanced degree preferred</li>\n<li>8+ years of experience based on education</li>\n<li>Expertise with software such as Simulia’s MODSIM, Abaqus, Optistruct, and Ansa. Also expertise with programming language software such as Matlab, Python, and Excel VBA.</li>\n<li>Expertise with creation of new CAE Models/Methods and performing verification and validation.</li>\n<li>Ability to present complex concepts as simple summaries</li>\n<li>Excellent communication and interpersonal skills</li>\n</ul>\n<p><strong>Working Conditions:</strong></p>\n<ul>\n<li>Work is primarily conducted at an office desk. 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They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.</p>\n<p>As a Senior Engineer in the R&amp;D department, you will be responsible for developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI. You will implement designs in C++, RTL, and SystemVerilog-DPIs, and collaborate with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments. You will also create and optimize use models and applications for various emulation projects, conduct thorough verification and validation processes to ensure the highest quality of emulation models, and provide technical guidance and mentorship to junior team members when necessary.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI.</li>\n<li>Implementing designs in C++, RTL, and SystemVerilog-DPIs.</li>\n<li>Collaborating with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments.</li>\n<li>Creating and optimizing use models and applications for various emulation projects.</li>\n<li>Conducting thorough verification and validation processes to ensure the highest quality of emulation models.</li>\n<li>Providing technical guidance and mentorship to junior team members when necessary.</li>\n</ul>\n<p>As a member of the Emulation Transactor Development Team, you will work closely with various teams across the organization to ensure the highest quality in our products. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.</p>\n<p>Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n<li>Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n<li>Support strategic customer engagements and help expand Synopsys&#39; presence in the semiconductor ecosystem through successful project outcomes.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.</li>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).</li>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimisation, STA, EMIR, and physical verification.</li>\n<li>Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.</li>\n<li>Strong scripting and automation skills using Python, PERL, TCL, or similar languages.</li>\n<li>Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.</li>\n<li>Exposure to high-frequency design and low-power design methodologies.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Proactive, self-motivated, and driven to achieve technical excellence.</li>\n<li>Exceptional problem-solving and analytical skills with a keen attention to detail.</li>\n<li>Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.</li>\n<li>Collaborative team player who values knowledge sharing and mentoring others.</li>\n<li>Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</p>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>** Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7c858523-91f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-engineering-staff-engineer/44408/92684730800","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimisation","static timing analysis (STA)","physical verification","block-level and full-chip floor-planning","EMIR analysis","timing closure","Python","PERL","TCL","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime"],"x-skills-preferred":["high-frequency design","low-power design methodologies","collaboration","problem-solving","analytical skills","communication","interpersonal abilities"],"datePosted":"2026-04-05T13:22:21.047Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimisation, static timing analysis (STA), physical verification, block-level and full-chip floor-planning, EMIR analysis, timing closure, Python, PERL, TCL, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, high-frequency design, low-power design methodologies, collaboration, problem-solving, analytical skills, communication, interpersonal abilities"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_106cfbf6-843"},"title":"Physical Design Specialist (PDS)","description":"<p>We&#39;re looking for a Physical Design Specialist (PDS) to join our team. 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We work closely with customers and internal teams, supporting them through every stage of their design journey and continually pushing the boundaries of what&#39;s possible in digital backend technology.</p>\n<p>As a Staff Engineer, you will have the opportunity to work on cutting-edge projects, develop your technical skills, and contribute to the growth and success of the company. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking an experienced IC physical design expert to lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Technically lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</li>\n<li>Guide signoff quality timing constraints development and qualification for critical Subsystem designs with hundreds of clocks.</li>\n<li>Drive PNR flow and methodology for timing critical muti-million deep sub-micro designs flat/hierarchical digital implementation.</li>\n<li>Handson expertise in all aspects of flat, hierarchical PNR implementation tasks like synthesis, floorplanning, design partitioning, DFT, low power/UPF based implementation, timing constraints, clock tree synthesis, routing and optimization, extraction, timing signoff, signal integrity, physical verification, Power &amp; IR drop signoff to debug and resolve critical implementation bottlenecks.</li>\n<li>Requires close interaction and collaborative teamwork with multiple functional groups front end, analog, PM/PEMs.</li>\n<li>Drive RTL, design partitioning, timing constraints related feedback to Frond-end team for data path optimization, clock &amp; reset architecture improvements for enabling high speed timing closure, PPA improvements.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You&#39;ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>16005</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>03/05/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are an accomplished and forward-thinking engineering professional with a deep passion for the intersection of artificial intelligence and semiconductor design. Your expertise spans RTL-to-GDSII flows, and you have hands-on experience with industry-leading EDA tools, especially those driving the next generation of AI and high-performance compute silicon. You are highly analytical, able to dissect complex design challenges and architect robust, scalable solutions that address both immediate and future technology needs. You thrive in customer-facing roles, translating requirements into actionable methodologies and championing innovation every step of the way.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.</li>\n</ul>\n<ul>\n<li>Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.</li>\n</ul>\n<ul>\n<li>Enabling and deploying flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, utilizing Tcl/Python scripting for automation.</li>\n</ul>\n<ul>\n<li>Collaborating cross-functionally with customers, R&amp;D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges.</li>\n</ul>\n<ul>\n<li>Leading and mentoring a team of junior application engineers, providing technical guidance, coaching, and project management support to ensure successful execution of deliverables.</li>\n</ul>\n<ul>\n<li>Delivering technical presentations, application notes, and best practices to both internal and external stakeholders, supporting knowledge-sharing and customer enablement.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate customer adoption of next-generation AI-driven design methodologies, empowering them to achieve breakthrough silicon results.</li>\n</ul>\n<ul>\n<li>Shape Synopsys’ technology direction by providing valuable field insights and partnering with R&amp;D on new feature development.</li>\n</ul>\n<ul>\n<li>Reduce time-to-market and improve competitiveness for customers through innovative flow optimization and automation.</li>\n</ul>\n<ul>\n<li>Drive Synopsys’ leadership in AI-powered EDA solutions, further differentiating our offerings in a competitive market.</li>\n</ul>\n<ul>\n<li>Elevate the technical capabilities of the application engineering team through mentorship and cross-training.</li>\n</ul>\n<ul>\n<li>Enhance customer satisfaction and loyalty through proactive engagement, expert troubleshooting, and tailored technical support.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5 + years of relevant experience.</li>\n</ul>\n<ul>\n<li>Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&amp;R tools (Fusion Compiler, ICC2, or similar).</li>\n</ul>\n<ul>\n<li>Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes.</li>\n</ul>\n<ul>\n<li>Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.</li>\n</ul>\n<ul>\n<li>Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.</li>\n</ul>\n<ul>\n<li>Outstanding verbal and written communication, presentation, and customer interaction skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative and empathetic leader, skilled at building relationships and enabling the success of others.</li>\n</ul>\n<ul>\n<li>Analytical thinker with a problem-solving mindset and a passion for continuous improvement.</li>\n</ul>\n<ul>\n<li>Adaptable and resilient in the face of evolving customer requirements and technology landscapes.</li>\n</ul>\n<ul>\n<li>Strong organizational skills, able to manage multiple projects and priorities with poise.</li>\n</ul>\n<ul>\n<li>Driven by curiosity and a desire to innovate at the forefront of AI and semiconductor design.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&amp;D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. With a culture rooted in collaboration, technical excellence, and mentorship, you’ll have the opportunity to lead, learn, and contribute to the next wave of EDA innovation.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_82b664ed-78c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/staff-application-engineer-backend/44408/92463617216","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL-to-GDSII flows","industry-leading EDA tools","physical synthesis","timing closure","clock tree synthesis (CTS)","routing at advanced technology nodes","Tcl and Python scripting","backend P&R tools","Fusion Compiler","ICC2"],"x-skills-preferred":[],"datePosted":"2026-03-08T22:22:03.259Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL-to-GDSII flows, industry-leading EDA tools, physical synthesis, timing closure, clock tree synthesis (CTS), routing at advanced technology nodes, Tcl and Python scripting, backend P&R tools, Fusion Compiler, ICC2"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_04934540-478"},"title":"Physical Design Specialist (PDS)","description":"<p>We are looking for a Physical Design Specialist (PDS) to join our team. In this role, you will be responsible for supporting the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>The primary focus of the Physical Design Specialist (PDS) is to support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</li>\n<li>In addition, PDS AEs will articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)</li>\n<li>RTL to GDSII full flow experience or knowledge is preferable</li>\n<li>Strong interest and understanding of Advanced Node &amp; Design methodologies are required.</li>\n<li>In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.</li>\n<li>Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred</li>\n<li>Excellent verbal and written presentation/communication skills are mandatory.</li>\n<li>Customer sensitivity, the ability to multiplex many issues &amp; set priorities, and the desire to help customers exploit new technologies are essential for success in the position.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_04934540-478","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/applications-engineering-principal-engineer/44408/90265976416","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Design Implementation experience","RTL to GDSII full flow experience","Strong interest and understanding of Advanced Node & Design methodologies","In-depth Synopsys Back end tool experience","Knowledge of several Clock Tree Synthesis methodologies","Excellent verbal and written presentation/communication skills","Customer sensitivity"],"x-skills-preferred":["BSEE or equivalent","Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus)","Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus)","Tool knowledge (preferred): STA (Primetime, Tempus)"],"datePosted":"2026-03-06T07:29:04.274Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Design Implementation experience, RTL to GDSII full flow experience, Strong interest and understanding of Advanced Node & Design methodologies, In-depth Synopsys Back end tool experience, Knowledge of several Clock Tree Synthesis methodologies, Excellent verbal and written presentation/communication skills, Customer sensitivity, BSEE or equivalent, Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus), Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus), Tool knowledge (preferred): STA (Primetime, Tempus)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_19f57d9e-523"},"title":"Staff EDA Applications Engineer","description":"<p>We are seeking a highly skilled Staff EDA Applications Engineer to join our team in Bengaluru, India. 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