You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

XML job scraping automation by YubHub

Your focus will be in the areas of design planning, floorplanning, place and route, parasitic extraction, signal integrity analysis and prevention, IR drop/EM analysis and physical verification (DRC/LVS).

A secondary focus will be in static timing analysis, Low Power Static check and formal verification. You will work as a member of the customer's IC design team, leveraging their experience and Synopsys' best practices to have immediate impact on their current project while transferring valuable knowledge for future projects.

You will interact regularly with customers to identify and eliminate barriers to project success. You will plan and manage delivery of own project-related tasks. You will leverage entire Synopsys team to ensure project success. You will provide feedback to R&D/AE on suggested tool enhancements or issues.

You will work with or as Project Leader to develop technical proposals, working through project life cycle and produce consistently high-quality technical solutions.

XML job scraping automation by YubHub

Key responsibilities include:

• Driving RTL-to-GDSII implementation for complex digital IP, ensuring signoff timing and PV closure.
• Leading backend flow development, including PnR, STA, DRC, LVS, and EMIR analysis.
• Collaborating with design, CAD, and cross-functional teams to optimize backend methodologies and resolve technical issues.
• Supporting project execution by troubleshooting timing, congestion, and physical verification challenges.

You will be part of the dynamic Design Support Group (DSG) at Synopsys, a passionate collective of engineers dedicated to delivering world-class backend solutions. Our team thrives on innovation, collaboration, and a shared commitment to technical excellence. We work closely with customers and internal teams, supporting them through every stage of their design journey and continually pushing the boundaries of what's possible in digital backend technology.

As a Staff Engineer, you will have the opportunity to work on cutting-edge projects, develop your technical skills, and contribute to the growth and success of the company. You will be part of a dynamic and supportive team that values innovation, collaboration, and technical excellence.

XML job scraping automation by YubHub

As a Sr Staff Engineer in Custom Analog Enablement and Methodology, you will propose and develop advanced layout design techniques and methodologies, including specification, prototyping, and building solutions with scripting languages (Tcl/Perl/Python). You will run verification on existing designs to assess PDK update impacts and create innovative scripts to minimize rework. You will collaborate with multiple organizations and teams across global time zones to ensure the design environment is optimized for IP design teams.

Key responsibilities include:

• Proposing and developing advanced layout design techniques and methodologies
• Running verification on existing designs to assess PDK update impacts
• Creating innovative scripts to minimize rework
• Collaborating with multiple organizations and teams across global time zones

The ideal candidate will have a deep understanding of custom analog layout design, especially with sub-5nm FinFet/Gate-All-Around nodes. You will be proficient in scripting languages: Tcl, Perl, and Python for workflow automation and prototyping. You will also have the ability to debug LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports effectively.

This role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

XML job scraping automation by YubHub

What you'll do

• Providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.
• Diagnosing, troubleshooting, and resolving complex technical issues during customer installations and deployments.
• Training customers on new implementations, features, and capabilities of Synopsys RTL2GDS full flow solutions.

What you need

• Extensive experience with RTL to GDSII full flow and advanced node design methodologies.
• Hands-on proficiency with synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis.

XML job scraping automation by YubHub

What you'll do

• Designing and integrating memory leafcells and standard cell layouts.
• Optimizing layouts for speed, area, and power.
• Running and debugging DRC, LVS, and ERC checks.
• Collaborating with circuit and verification engineers.

What you need

• 2+ years in custom, standard cell, or memory layout design.
• Experience with FinFET, DRC, LVS, ERC, and boundary conditions.
• Proficiency in Custom Compiler, ICV, and scripting (Perl, Shell, TCL).

XML job scraping automation by YubHub

What you'll do

• Designing and implementing custom analog layout for high-speed SERDES blocks, including TX, RX, and PLLs, in advanced technology nodes.
• Developing floor plans, optimizing power distribution networks, and executing signal routing strategies with a focus on EMIR, parasitic minimization, and yield improvement.

What you need

• 5+ years of hands-on experience in custom analog layout, with a focus on High-Speed SERDES (TX/RX/PLL) in deep submicron technologies.
• Proficiency in floor planning, power grid design, signal routing, and parasitic optimization.
• Expertise in industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor Calibre, Synopsys IC Compiler).
• Strong understanding of EMIR, DRC, LVS, ERC, ANT, ESD, DFM, and PERC verification methodologies.

XML job scraping automation by YubHub

What you'll do

Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.

• Synthesis
• LEC
• LDRC
• GCA
• STA
• PTPX

What you need

• 2 - 4 years of related experience.
• Good of ASIC/SOC design, synthesis, timing closure.
• Familiar with Synthesis, LEC, STA flow.
• It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.
• Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.
• Familiar with scripting languages, such as TCL, Perl, Python.
• Good English/communication skills and willingness to work with customer.
• BS or MS with an EE or related major

XML job scraping automation by YubHub

What you'll do

Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.

• Synthesis
• LEC
• LDRC
• GCA
• STA
• PTPX

What you need

• 6-12 years of related experience.
• Good of ASIC/SOC design, synthesis, timing closure.
• Familiar with Synthesis, LEC, STA flow.
• It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.
• Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.
• Familiar with scripting languages, such as TCL, Perl, Python.
• Good English/communication skills and willingness to work with customer.
• BS or MS with an EE or related major

XML job scraping automation by YubHub

What you'll do

Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.

• Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.

• Drive flow development and optimization to improve design quality and predictability.

• Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).

• Contribute to the adoption and integration of advanced technologies and tool features in design implementation.

• Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.

• Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.

What you need

• Minimum 7 years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why this matters

Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.

Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.

Enhance the predictability and simplicity of implementation processes for complex interface IPs.

Accelerate the adoption of next-generation design technologies and tools across the industry.

Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.

Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.

What you’ll need

• Minimum 7years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why you’ll love this role

• Collaborate with a talented team of engineers and experts to drive innovation and excellence in chip design and IP integration.

• Work on cutting-edge technologies and tools, shaping the future of the semiconductor industry.

• Enjoy a dynamic and supportive work environment that fosters growth, learning, and collaboration.

• Participate in professional development opportunities to enhance your skills and expertise.

• Contribute to the development of best-in-class methodologies and tools that drive industry-leading results.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

• In addition to company holidays, we have ETO and FTO Programs.

• Family Support

• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Retirement Plans

• Save for your future with our retirement plans that vary by region and country.

• Compensation

• Competitive salaries.

• Awards

• We're proud to receive several recognitions.

• Explore the Possibilities with Synopsys

• Search Synopsys Careers

• Join our Talent Community

XML job scraping automation by YubHub

What you'll do

Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.

• Demonstrating the unique advantages and capabilities of Synopsys' industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.

What you need

Bachelor's and/or Master's degree in Electrical Engineering or a related field.

XML job scraping automation by YubHub

Gestalte mit uns die Steuerfunktion der Zukunft! In einer Zeit, in der Regierungen weltweit auf digitale Melde- und Rechnungsformate setzen, sind technologische Lösungen gefragt, die Rechtssicherheit, Automatisierung und Skalierbarkeit gewährleisten. Als (Senior) Manager im Bereich Tax mit Fokus SAP DRC hast du die Möglichkeit, gemeinsam mit unserem Tax Technology Team ein dynamisch wachsendes Lösungsportfolio rund um Statutory Reporting und E-Invoicing zu gestalten und ein fachlich starkes Team aufzubauen – für komplexe nationale wie auch internationale Anforderungen.

What you need

Um für deinen Weg bei MHP gewappnet zu sein, hast du folgende Qualifikationen im Gepäck:

• Abgeschlossenes Studium oder eine vergleichbare Ausbildung sowie mindestens fünf Jahre Berufserfahrung im Tax Technology Umfeld
• Leidenschaft für zukunftsweisende IT-Technologien & steuerlichen Anforderungen im Indirect Tax/Compliance Bereich
• Expertise in der Implementierung mit SAP DRC, SAP S/4HANA und steuerlichen Meldepflichten sowie ein technisches Verständnis für Systemarchitektur und Schnittstellen.

Why this matters

Bei MHP wächst du in einem innovativen und fördernden Umfeld kontinuierlich an deinen Aufgaben. Das macht uns zum perfekten Sparring-Partner für deine Karriere. Sowohl für fachlichen Input als auch berufliches Networking.

XML job scraping automation by YubHub

Gestalte mit uns die Steuerfunktion der Zukunft! In einer Zeit, in der Regierungen weltweit auf digitale Melde- und Rechnungsformate setzen, sind technologische Lösungen gefragt, die Rechtssicherheit, Automatisierung und Skalierbarkeit gewährleisten. Als Senior SAP DRC Spezialist:in hast du die Möglichkeit, gemeinsam mit unserem Tax Technology Team ein dynamisch wachsendes Lösungsportfolio rund um Statutory Reporting und E-Invoicing zu gestalten – für komplexe nationale wie auch internationale Anforderungen.

What you need

Um für deinen Weg bei MHP gewappnet zu sein, hast du folgende Qualifikationen im Gepäck:

• Abgeschlossenes Studium oder eine Ausbildung mit anschließender Erfahrung im Tax Umfeld
• Leidenschaft für zukunftsweisende IT-Technologien & steuerlichen Anforderungen im Indirect Tax/Compliance Bereich
• Expertise in der Implementierung mit SAP DRC, SAP S/4HANA und steuerlichen Meldepflichten sowie ein technisches Verständnis für Systemarchitektur und Schnittstellen

Why this matters

Bei MHP wächst du in einem innovativen und fördernden Umfeld kontinuierlich an deinen Aufgaben. Das macht uns zum perfekten Sparring-Partner für deine Karriere. Sowohl für fachlichen Input als auch berufliches Networking.

XML job scraping automation by YubHub