{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/display-port"},"x-facet":{"type":"skill","slug":"display-port","display":"Display Port","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c01e313a-c5a"},"title":"IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer","description":"<p>We&#39;re looking for an IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer to join our team.</p>\n<p>Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.</li>\n<li>Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.</li>\n<li>Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum 5+ years of experience in IP/ASIC/SOC design implementation.</li>\n<li>Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.</li>\n<li>Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.</li>\n<li>Good communication skills while interacting with internal teams and customers.</li>\n</ul>\n<p>Preferred Experience:</p>\n<ul>\n<li>Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.</li>\n<li>Experience in DesignWare Core IPs or PHYs.</li>\n<li>Experience in TCL, Perl, Python, or other shell scripting.</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Competitive salary and benefits package.</li>\n<li>Opportunities for professional growth and development.</li>\n<li>Collaborative and dynamic work environment.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c01e313a-c5a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/shanghai/ip-pcie-cxl-usb-dp-subsystem-design-implementation-engineer/44408/92638132304","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["IP/ASIC/SOC design implementation","synthesis","timing optimization","SDC writing","CDC/RDC checking","PCIe","USB","Display Port","Ethernet","DDR"],"x-skills-preferred":["Design Compiler","Fusion Compiler","PrimeTime","Spyglass","VC Spyglass","DesignWare Core IPs","PHYs","TCL","Perl","Python","shell scripting"],"datePosted":"2026-04-05T13:22:43.150Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Shanghai"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"IP/ASIC/SOC design implementation, synthesis, timing optimization, SDC writing, CDC/RDC checking, PCIe, USB, Display Port, Ethernet, DDR, Design Compiler, Fusion Compiler, PrimeTime, Spyglass, VC Spyglass, DesignWare Core IPs, PHYs, TCL, Perl, Python, shell scripting"}]}