This role is for a Pre-Silicon Signoff Lead who will be responsible for leading simulation and sign-off activities that guarantee reliability and performance. The ideal candidate will have a rich background in high-speed serial communication and advanced transceiver design, with expertise in theoretical modeling and hands-on lab work.

Key responsibilities include collaborating closely with analog, digital, and hardware teams to ensure comprehensive design and verification coverage, developing and maintaining robust simulation and verification plans for IP, and reviewing progress against verification plans through regular meetings with multiple verification teams.

The successful candidate will have a strong command of simulation, verification, and hardware validation processes, with experience in high-speed protocols such as PCIe and Ethernet. They will also have a proven track record of leadership in testbench architecture, planning, cross-site collaboration, and mentoring.

As a member of our world-class engineering team, you will drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications.

If you are an innovative and forward-thinking engineer with a passion for advancing connectivity technologies, we encourage you to apply for this exciting opportunity.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement.

What You'll Be Doing:

• Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
• Creating and executing detailed test plans to verify complex ASIC designs.
• Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.
• Collaborating with design and architecture teams to identify and fix bugs.
• Performing functional coverage analysis and driving coverage closure.
• Mentoring and guiding junior verification engineers in best practices and methodologies.

The Impact You Will Have:

• Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.
• Enhancing the robustness and efficiency of our verification processes and methodologies.
• Contributing to the successful launch of Interface IP products, impacting various industries.
• Driving innovation and excellence within the verification team.
• Improving the overall performance and functionality of Synopsys' IP offerings.
• Fostering a culture of continuous improvement and technical excellence.

What You'll Need:

• Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet.
• Proficiency in SystemVerilog and UVM methodologies.
• Strong understanding of digital design and verification concepts.
• Experience with simulation tools such as VCS, ModelSim, or similar.
• Excellent problem-solving skills and attention to detail.

Who You Are:

• Detail-oriented with a strong analytical mindset.
• Excellent communicator, able to convey complex technical concepts clearly.
• Collaborative team player who thrives in a dynamic environment.
• Proactive and self-motivated, with a commitment to continuous learning.
• Mentor and leader, capable of guiding and developing junior engineers.

The Team You'll Be A Part Of:

You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Your proactive approach and problem-solving abilities make you a trusted advisor for both internal stakeholders and external customers. You are detail-oriented, yet able to see the big picture, ensuring that every design meets rigorous standards for quality, performance, and scalability. You enjoy guiding teams through challenging technical obstacles and are always eager to explore new technologies and methodologies that can enhance product development. Your communication skills are top-notch, enabling you to clearly articulate complex concepts to diverse audiences. You value inclusion and respect, fostering a team culture where every voice is heard and every idea is considered.

Role Details

• Oversee junior engineers and lead the design, implementation, verification, and physical synthesis of NVM controllers for OTP and MTP products at advanced technology nodes.
• Provide digital guidance for new product developments, ensuring robust architecture and innovative solutions.
• Manage the maintenance and enhancement of digital control blocks, chip test systems, circuit models, and design-for-test circuits.
• Participate in all phases of the ASIC design cycle, including architecture definition, modeling, RTL coding, verification, synthesis, and place & routing.
• Deliver technical support to internal teams, application engineers, and customers during product integration phases.
• Collaborate with cross-functional teams to optimize design flows and ensure seamless integration of digital components.
• Drive continuous improvement initiatives and promote best practices in digital design and verification methodologies.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.

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What you'll do

• Leading and managing a team of ASIC Digital Verification engineers, providing guidance and mentorship;
• Creating and maintaining testbenches using SystemVerilog and UVM methodologies;

What you need

• Extensive experience in ASIC digital verification, particularly with HBM (or DDR/LPDDR) protocols;
• Proficiency in SystemVerilog, UVM, and other verification tools and methodologies;

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What you'll do

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

• Designing, implementing and optimizing verification environments to ensure the correctness of Interface IP protocols.
• Creating, executing and tracking against detailed test plans to verify complex ASIC designs.

What you need

• Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).
• Proficiency in System Verilog, SVA and UVM methodologies.
• Strong understanding of digital design and verification concepts.
• Familiarity with wider digital ASIC and IP development flow, including RTL design through synthesis.
• Experience with simulation tools such as VCS, Model Sim, or similar.
• Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.
• Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.

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What you'll do

Collaborating closely with analog, digital, and hardware teams to ensure holistic design and verification coverage.

• Developing and maintaining comprehensive simulation and verification plans for IP, aligning with reliability and performance targets.

What you need

• MSc or PhD in Electrical/Computer Engineering, with 10+ years of relevant industry experience.

Why this matters

Advance high-speed connectivity for enterprise and hyperscale applications worldwide.

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What you'll do

• Develop and maintain high-quality digital verification environments, including UVM, SystemVerilog, and C++.
• Collaborate with cross-functional teams to develop and verify complex digital designs.
• Identify and prioritize verification tasks to meet project timelines and quality standards.
• Develop and execute verification plans, including testbenches, test cases, and coverage metrics.
• Collaborate with design teams to develop and verify complex digital designs.

What you need

• Bachelor's degree in Computer Science, Electrical Engineering, or related field.
• 10+ years of experience in digital verification, including UVM, SystemVerilog, and C++.
• Strong understanding of digital design principles and verification methodologies.
• Excellent communication and collaboration skills.
• Experience with Agile development methodologies and version control systems.

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