As a Lead RTL Design Engineer, you will be responsible for leading RTL design and implementation for high-performance mixed signal IPs including UCIe, DDR, and Die-to-Die interfaces. You will take technical ownership of assigned blocks, developing architecture and microarchitecture, and driving design reviews.

Key responsibilities include:

• Leading RTL design and implementation for high-performance mixed signal IPs
• Taking technical ownership of assigned blocks, developing architecture and microarchitecture, and driving design reviews
• Specifying, architecting, and implementing digital logic using Verilog/SystemVerilog
• Collaborating with circuit design, verification, physical design, and validation teams to ensure design closure and integration
• Driving logic synthesis, lint, clock domain crossing (CDC), design-for-test (DFT), and timing closure for your blocks
• Analyzing coverage, debugging functional and timing issues, supporting integration, and authoring technical documentation

In this role, you will contribute to Synopsys' reputation as a leader in advanced semiconductor design solutions. You will drive innovation in digital design and architecture, influencing key product features and capabilities. You will ensure the delivery of high-quality, reliable, and scalable IPs that meet stringent market requirements.

As a leader, you will foster a culture of continuous learning, inclusivity, and creative thinking, empowering your peers and advancing the team's collective success. You will be motivated by working on cutting-edge IPs such as UCIe, DDR, and Die-to-Die interfaces, and you will stay current with industry trends and emerging technologies, including AI/ML.

You will join a dynamic, high-performing engineering team at Synopsys Bangalore, focused on designing and delivering advanced mixed signal IPs for leading-edge semiconductor applications. The team prides itself on technical excellence, collaboration, and innovation, working closely with global counterparts across design, verification, and product engineering.

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You will develop and optimize software for Zebu Server emulation, collaborate with global teams in compiler, timing, and performance areas, brainstorm and implement innovative solutions for FPGA emulation challenges, benchmark new features and validate improvements, and document and communicate technical progress.

Your contributions will advance Zebu Server's capacity and performance, help customers design and verify large SOC chips, accelerate time-to-market for smart devices, and drive innovation in emulation workflows.

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What you'll do

You will lead and deliver multi-project functionality for each VC Formal product release as a technical expert and initiative owner.

• Designing, implementing, and testing complex algorithms and data structures for high-performance formal verification solutions.
• Driving technical initiatives, collaborating with peers and management to sell and execute the vision for formal verification advancements.
• Identifying broad objectives and developing strategies to solve open-ended, challenging problems in software development.
• Running effective meetings to facilitate team problem-solving and helping overcome technical roadblocks (“brick walls”).
• Collaborating with global cross-functional teams to define, implement, and deliver innovative verification solutions.
• Ensuring the quality, robustness, and efficiency of software implementations in a large-scale development environment.
• Prioritizing project milestones and features, and developing project schedules with minimal managerial direction.

What you need

• BS/MS in Computer Science or related field, with 5+ years of relevant experience in software development.
• Expertise in C/C++ programming, with a demonstrated ability to write efficient, maintainable code.
• Strong foundation in algorithms and data structure design, with practical implementation experience.
• Proficiency in software development processes, debugging, and configuration management tools.
• Solid understanding of digital logic; prior experience in EDA, equivalence checking, or formal technologies is a plus.

Why this matters

Accelerate the verification of complex SoC designs, enabling Synopsys customers to deliver innovative products to market faster.

• Shape the development of next-generation formal verification algorithms and methodologies, setting industry benchmarks.
• Enhance the scalability and performance of VC Formal, ensuring it remains the tool of choice for the most challenging design tasks.
• Drive technical excellence and foster a culture of innovation within the R&D team and across the organization.
• Mentor and inspire fellow engineers by sharing best practices and facilitating knowledge transfer.
• Contribute to the overall success of Synopsys by delivering reliable, high-quality software that meets and exceeds customer expectations.

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