e6ae0653-f7e ASIC Digital Design, Sr. Engineer Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

As a Principal ASIC Digital Design Engineer, you are a trailblazer who thrives in dynamic environments and is passionate about pushing the boundaries of semiconductor technology. You bring a deep understanding of digital design methodologies, paired with a creative approach to problem-solving and a tenacious drive to deliver robust solutions.

You are not only technically proficient in RTL coding and digital verification, but you also bring a practical understanding of synthesis flows, DFT, and production testing. Your scripting skills in Shell, Perl, Python, and TCL enable you to automate tasks and streamline development workflows.

You will design and verify advanced digital circuits for PAM-based SerDes PHY IP, ensuring robust and high-performance mixed-signal solutions. You will develop RTL code, model analog blocks, and craft complex system-level testbenches in Verilog to validate functionality and performance.

You will collaborate with Application Engineers, Analog, and P&R teams to resolve technical issues, provide customer support, and ensure successful product deployment. You will mentor junior engineers, foster knowledge sharing, and contribute to a culture of innovation and continuous improvement.

You will drive the development of next-generation SerDes solutions, powering high-speed data transmission in cutting-edge applications. You will enable customers to achieve superior performance and reliability in their semiconductor products through innovative digital design.

You will need a Bachelor's or Master's degree in Electrical Engineering (BSEE or MSEE) with at least 10 years of industry experience in digital design and verification. You must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is required. You must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows. Scripting experience in Shell, Perl, Python, and TCL is a plus.

You will join a highly experienced mixed-signal design and verification team, focused on advancing the capabilities of PAM-based SerDes products. The team is comprised of digital and mixed-signal engineers who work collaboratively from specification development through prototype testing.

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]]> full-time senior onsite Verilog, VCS, Digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows, Shell, Perl, Python, TCL, RTL coding, Modeling of analog blocks, Writing complex system-level testbenches in Verilog, Defining synthesis design constraints, Resolving STA issues, Gate-level simulation failures, Clock/Reset domain crossing design constraints, Evaluating violations using CDC/RDC tools, Enhancing and maintaining existing SERDES PHY IPs, Interacting with Application Engineers for customer support Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is a leading electronic design automation (EDA) software company that provides tools, services, and intellectual property (IP) for designing and verifying semiconductor chips and systems. https://careers.synopsys.com https://careers.synopsys.com/job/mississauga/asic-digital-design-sr-engineer-14687/44408/91568840256 Mississauga 2026-04-24 91d6c431-900 Digital Design Verification Engineer We are seeking a detail-focused engineer with strong digital design and verification skills to join our team. As a Digital Design Verification Engineer, you will be responsible for ensuring reliable, high-quality silicon products. Your primary focus will be on writing block-level test-cases, including constrained directed random tests, and verifying digital designs using SystemVerilog and UVM.

Key responsibilities:

  • Write test-cases for digital designs using SystemVerilog and UVM
  • Verify digital designs using constrained directed random tests
  • Collaborate with design teams to resolve issues and improve design quality
  • Develop and maintain test benches and test scripts
  • Participate in code reviews and contribute to the improvement of the verification environment

Requirements:

  • BSEE or MSEE degree
  • Minimum 1 year of experience in digital design and verification
  • Strong knowledge of SystemVerilog and UVM
  • Experience with constrained directed random tests
  • Good communication and teamwork skills

Preferred qualifications:

  • Knowledge of back-end synthesis tools DC/PT
  • Experience with scripting languages such as Perl, Python, and TCL
  • Familiarity with digital design methodologies and ATE production testing

As a member of our team, you will have the opportunity to work on cutting-edge projects and collaborate with experienced engineers. We offer a comprehensive range of health, wellness, and financial benefits, as well as opportunities for professional growth and development.

If you are a motivated and detail-focused engineer with a passion for digital design and verification, we encourage you to apply for this exciting opportunity.

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]]> full-time mid onsite SystemVerilog, UVM, digital design, verification, test-cases, constrained directed random tests, back-end synthesis tools DC/PT, scripting languages, digital design methodologies, ATE production testing Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is a leading provider of electronic design automation (EDA) software and intellectual property (IP) used in the design and manufacturing of semiconductors. https://careers.synopsys.com https://careers.synopsys.com/job/ottawa/digital-design-verification-engineer-14915/44408/93816739392 Ottawa 2026-04-24