We are seeking a senior verification leader to drive the strategy, execution, and quality of next-generation PCIe PHY IP verification. As a Principal Engineer, you will define and drive the verification strategy and functional quality for next-generation PCIe PHY IPs.

Key Responsibilities:

• Define and drive the verification strategy and functional quality for next-generation PCIe PHY IPs.
• Develop comprehensive verification plans for complex mixed-signal digital designs with primary emphasis on PCIe PHY functionality and protocol compliance.
• Architect, develop, and execute advanced testbench environments for block-level and subsystem-level verification.
• Verify key PCIe PHY features such as LTSSM behavior, PIPE interface interactions, link initialization and training, power management, equalization flows, error handling, and compliance-related scenarios.
• Work closely with design, analog, firmware, architecture, and validation teams to ensure robust coverage of cross-functional use cases.
• Use advanced verification methodologies, including constrained-random, assertion-based verification, coverage-driven verification, and debug automation, to achieve high-quality results.
• Analyze failures, root-cause complex issues, and drive resolution across design and verification domains.
• Mentor and guide other engineers, promote verification best practices, and help build a culture of technical excellence and continuous improvement.

Impact:

• Elevate the quality and reliability of PCIe PHY IP solutions, ensuring industry-leading performance and compliance.
• Accelerate time-to-market for customers by enabling robust verification coverage and efficient execution.
• Drive innovation in verification methodologies and environments, setting new standards for mixed-signal IP verification.
• Strengthen cross-team collaboration, integrating expertise from design, analog, firmware, and architecture groups.
• Mentor and empower peers, building a highly skilled and motivated verification team.
• Enhance customer satisfaction and trust by delivering high-quality IP products that meet demanding requirements.

Requirements:

• Extensive experience in mixed-signal ASIC/IP verification.
• Strong expertise in PCIe and PCIe PHY verification.
• Solid understanding of high-speed SerDes/PHY architecture and digital control verification in mixed-signal environments.
• Hands-on experience with modern verification methodologies such as SystemVerilog, UVM, assertions, and coverage-driven verification.
• Experience developing verification plans, building reusable verification environments, and closing coverage for complex IP products.
• Strong debugging and problem-solving skills, with the ability to work independently and drive issues to closure.
• Excellent communication and collaboration skills for working across global, cross-functional teams.
• Proven ability to mentor engineers and lead technical verification activities.

Team:

You'll join a world-class group of engineers dedicated to advancing high-speed silicon IP solutions. Our team specializes in PCIe PHY technology, collaborating across design, analog, firmware, architecture, and validation disciplines to deliver IP products that set industry benchmarks for performance, power efficiency, and reliability.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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