We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are a passionate and detail-oriented ASIC Digital Design professional who thrives in high-tech, fast-paced environments. With a strong foundation in Design-for-Testability (DFT) methodologies, you enjoy taking ownership of complex challenges and delivering reliable, high-quality results. You are eager to collaborate with diverse, global teams and are driven by a desire to continuously learn and grow within the semiconductor industry. Your expertise in scan insertion, ATPG, and scan STA is matched by your ability to adapt to new tools and technologies. You value open communication, inclusivity, and knowledge sharing, and you excel at translating intricate technical concepts into actionable solutions. As a proactive problem solver, you are comfortable navigating ambiguity and take pride in mentoring junior engineers while contributing to collective team success. You are committed to upholding Synopsys' culture of innovation, integrity, and excellence, and you are excited about building next-generation semiconductor products that fuel advances in AI, automotive, and beyond.

What You'll Be Doing:

• Lead and execute scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex ASIC designs.
• Work closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle.
• Analyze and resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability.
• Perform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths.
• Collaborate with cross-functional teams to define and implement best practices for DFT methodologies and flows.
• Contribute to the continuous improvement of automation scripts and design flows to boost efficiency and reduce turnaround time.

The Impact You Will Have:

• Enhance the testability and reliability of cutting-edge ASIC products, reducing defect rates and improving time-to-market.
• Drive innovation in DFT flows, setting new standards for quality and efficiency within the organization.
• Enable successful silicon validation and ramp-up, directly contributing to customer satisfaction and business growth.
• Represent Synopsys as a technical leader in the industry, influencing best practices and future technology directions.
• Empower cross-functional teams by sharing expertise, fostering a culture of continuous improvement and collaboration.
• Contribute to the development of next-generation technologies in AI, automotive, and other high-impact sectors.

What You'll Need:

• Extensive hands-on experience with DFT methodologies, including scan insertion and ATPG for complex ASIC designs.
• Proficiency with industry-standard EDA tools such as Spyglass DFT and scan STA analysis suites.
• Strong understanding of digital logic design, RTL coding, and verification principles.
• Demonstrated ability to debug and resolve DFT-related issues across multiple project phases.
• Solid scripting skills (e.g., TCL, Perl, Python) to automate design and test flows.

Who You Are:

• Collaborative team player who communicates effectively across functions and cultures.
• Proactive problem solver, comfortable with ambiguity and rapid change.
• Detail-oriented and highly organized, with a commitment to delivering high-quality results.
• Inclusive and open-minded, eager to share knowledge and mentor others.
• Self-motivated and driven by curiosity, with a continuous learning mindset.

The Team You'll Be A Part Of: You will join a dynamic and innovative DFT team within Synopsys' Engineering organization in Bangalore. The team is dedicated to advancing ASIC testability and reliability, working collaboratively with design, verification, and software groups across the globe. Our culture values technical excellence, mentorship, and cross-disciplinary innovation, providing opportunities to work on industry-leading products that power the next wave of intelligent systems.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What you'll do

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

• Leading digital design and verification activities for advanced SERDES products, including Backplane Ethernet, PCIe, SATA, and USB 2/3.
• Analyzing and interpreting digital and analog specifications, ensuring seamless integration in mixed-signal environments.

What you need

• MSEE (preferred) or equivalent with a minimum of 5 years' experience in digital design and verification.
• Proven proficiency in Verilog or VHDL for ASIC development.
• Experience with code quality metrics and coverage-driven verification methodologies.
• In-depth knowledge of high-speed digital and mixed-signal design, asynchronous clock crossings, and DFT methodologies.
• Strong understanding of CDC, synthesis, and power optimization techniques.
• Hands-on experience with simulation tools and collaborative debugging in verification environments.
• Ability to develop system-level specifications for complex digital and analog systems.

What you'll be doing:

• Leading digital design and verification activities for advanced SERDES products, including Backplane Ethernet, PCIe, SATA, and USB 2/3.
• Analyzing and interpreting digital and analog specifications, ensuring seamless integration in mixed-signal environments.
• Driving the creation, execution, and tracking of comprehensive test plans, including functional, assertion, and code coverage metrics.
• Overseeing design flows for clock domain crossing (CDC), synthesis, design-for-test (DFT), and low-power methodologies.
• Collaborating closely with verification teams to debug issues, analyze failure cases, and run gate-level simulations.
• Coordinating with cross-functional teams and providing technical leadership throughout the product lifecycle, from specification development to performance testing of test chips.
• Mentoring and developing junior engineers, fostering a culture of continuous learning and innovation.

The Impact You Will Have:

• Accelerate the delivery of industry-leading mixed-signal ASIC solutions, enabling next-generation connectivity standards.
• Enhance the quality and reliability of high-speed SERDES products through rigorous design and verification practices.
• Drive process improvements that elevate team productivity and product performance.
• Champion best practices in digital and mixed-signal design, setting new benchmarks for quality and efficiency.
• Foster a collaborative and innovative team environment, empowering engineers to reach their full potential.
• Strengthen Synopsys' reputation as a global leader in semiconductor technology through successful project execution and customer satisfaction.

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