As a Principal ASIC Digital Design Engineer, you are a trailblazer who thrives in dynamic environments and is passionate about pushing the boundaries of semiconductor technology. You bring a deep understanding of digital design methodologies, paired with a creative approach to problem-solving and a tenacious drive to deliver robust solutions.

You are not only technically proficient in RTL coding and digital verification, but you also bring a practical understanding of synthesis flows, DFT, and production testing. Your scripting skills in Shell, Perl, Python, and TCL enable you to automate tasks and streamline development workflows.

You will design and verify advanced digital circuits for PAM-based SerDes PHY IP, ensuring robust and high-performance mixed-signal solutions. You will develop RTL code, model analog blocks, and craft complex system-level testbenches in Verilog to validate functionality and performance.

You will collaborate with Application Engineers, Analog, and P&R teams to resolve technical issues, provide customer support, and ensure successful product deployment. You will mentor junior engineers, foster knowledge sharing, and contribute to a culture of innovation and continuous improvement.

You will drive the development of next-generation SerDes solutions, powering high-speed data transmission in cutting-edge applications. You will enable customers to achieve superior performance and reliability in their semiconductor products through innovative digital design.

You will need a Bachelor's or Master's degree in Electrical Engineering (BSEE or MSEE) with at least 10 years of industry experience in digital design and verification. You must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is required. You must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows. Scripting experience in Shell, Perl, Python, and TCL is a plus.

You will join a highly experienced mixed-signal design and verification team, focused on advancing the capabilities of PAM-based SerDes products. The team is comprised of digital and mixed-signal engineers who work collaboratively from specification development through prototype testing.

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Key responsibilities:

• Write test-cases for digital designs using SystemVerilog and UVM
• Verify digital designs using constrained directed random tests
• Collaborate with design teams to resolve issues and improve design quality
• Develop and maintain test benches and test scripts
• Participate in code reviews and contribute to the improvement of the verification environment

Requirements:

• BSEE or MSEE degree
• Minimum 1 year of experience in digital design and verification
• Strong knowledge of SystemVerilog and UVM
• Experience with constrained directed random tests
• Good communication and teamwork skills

Preferred qualifications:

• Knowledge of back-end synthesis tools DC/PT
• Experience with scripting languages such as Perl, Python, and TCL
• Familiarity with digital design methodologies and ATE production testing

As a member of our team, you will have the opportunity to work on cutting-edge projects and collaborate with experienced engineers. We offer a comprehensive range of health, wellness, and financial benefits, as well as opportunities for professional growth and development.

If you are a motivated and detail-focused engineer with a passion for digital design and verification, we encourage you to apply for this exciting opportunity.

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As a Sr Staff Engineer in SOC Engineering, you will independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs. You will execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.

Key Responsibilities:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm)
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence
• Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency

Key Requirements:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm)
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs
• Exposure to high-frequency design and low-power design methodologies

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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You Are: You are a passionate engineer with a strong foundation in analog and mixed-signal circuit design, eager to make a tangible impact in the world of semiconductor innovation. You thrive in collaborative environments, working alongside diverse teams to solve complex technical challenges. With 2+yrs experience and a solid academic background in Electronics or Electrical Engineering, you bring a keen understanding of CMOS processes and are adept at navigating deep submicron technologies.

What You'll Be Doing: Designing DDR/HBM Memory Interface I/O circuits, including GPIO and Special IOs, ensuring optimal performance and reliability. Collaborating with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project goals. Executing circuit design tasks with a focus on quality, efficiency, and adherence to industry standards. Developing and refining analog/mixed signal circuitry, leveraging advanced CMOS technologies and layout methodologies. Contributing to the ASIC design flow, from concept to implementation, including verification and documentation. Communicating effectively with internal development teams, providing technical insights and feedback throughout the design process. Participating in design reviews, troubleshooting, and optimization activities to ensure robust and scalable solutions.

The Impact You Will Have: Accelerate the development of high-performance memory interfaces, integral to next-generation computing platforms. Enhance product quality and reliability by applying best practices in analog circuit design and layout. Drive innovation in deep submicron CMOS technologies, enabling advanced chip functionalities. Contribute to Synopsys' leadership in DDR/HBM IP solutions, helping customers achieve breakthrough results. Foster a culture of collaboration and technical excellence across multidisciplinary teams. Support the delivery of robust, standards-compliant IP that powers industry-leading silicon solutions. Enable seamless integration and performance optimization for customers worldwide.

What You'll Need: B.Tech/M.Tech degree in Electronics or Electrical Engineering. 2+ years of hands-on experience in CMOS circuit design, preferably with exposure to deep submicron process technologies. Proficiency in analog/mixed signal design methodologies and layout flows. Familiarity with JEDEC DDR interface requirements, DDR Timing, ODT, and SDRAM functionality is a strong plus. Basic understanding of ESD concepts and ASIC design flow. Demonstrated ability to execute assigned circuit design tasks with high quality and efficiency. Strong written and verbal communication skills for effective team interactions.

Who You Are: Analytical thinker with strong problem-solving skills. Collaborative and adaptable, thriving in dynamic team settings. Detail-oriented and quality-driven, with a commitment to excellence. Proactive, self-motivated, and eager to learn new technologies. Effective communicator, capable of conveying technical concepts clearly. Resilient and resourceful, able to navigate complex challenges.

The Team You'll Be A Part Of: You will join a highly skilled engineering team specializing in DR I/O circuit design for memory interfaces. The team is focused on developing innovative DDR/HBM solutions, collaborating closely with PHY, package, and system engineers. Together, you will drive advancements in chip performance, reliability, and integration, shaping the future of semiconductor technology.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Staff R&D Software Engineer, you will design and develop advanced RTL analysis, restructuring, and optimization technologies within RTL Architect. You will implement efficient algorithms and data structures to enhance quality of results (QoR) and performance of architectural exploration tools. You will collaborate with product teams to integrate new features and support customer-driven requirements.

Key responsibilities include:

• Designing and developing advanced RTL analysis, restructuring, and optimization technologies within RTL Architect.
• Implementing efficient algorithms and data structures to enhance quality of results (QoR) and performance of architectural exploration tools.
• Collaborating with product teams to integrate new features and support customer-driven requirements.
• Utilizing AI productivity tools such as cursor and GitHub Copilot to accelerate development cycles and improve code quality.
• Conducting rigorous testing and validation of software modules to ensure reliability and scalability.

You will work closely with cross-functional teams to achieve common goals and foster a collaborative and inclusive engineering environment that empowers team members to achieve their best.

You will have the opportunity to work on challenging projects, apply analytical thinking to drive innovation, and leverage AI productivity tools to enhance your workflow. You will also have the chance to mentor and guide junior engineers, fostering a culture of innovation and technical excellence.

The ideal candidate will have a strong proficiency in C/C++ and object-oriented design principles, with 4 to 10 years of experience in EDA Software development. You will have a solid understanding of data structures, graphs, and algorithms, as well as expertise in RTL design methodologies (Verilog, SystemVerilog, VHDL).

You will be a self-driven individual with the ability to work independently and take initiative, a collaborative team player who enjoys mentoring others, and an excellent communicator who can convey technical concepts clearly.

You will be adaptable and eager to learn new technologies and methodologies, committed to fostering an inclusive and innovative work environment, and passionate about delivering high-quality, high-performance solutions that make a tangible impact on end users.

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Our team is focused on developing innovative DDR/HBM solutions, collaborating closely with PHY, package, and system engineers. Together, you will drive advancements in chip performance, reliability, and integration, shaping the future of semiconductor technology.

Key Responsibilities:

• Designing DDR/HBM Memory Interface I/O circuits, including GPIO and Special IOs, ensuring optimal performance and reliability.
• Collaborating with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project goals.
• Executing circuit design tasks with a focus on quality, efficiency, and adherence to industry standards.
• Developing and refining analog/mixed signal circuitry, leveraging advanced CMOS technologies and layout methodologies.
• Contributing to the ASIC design flow, from concept to implementation, including verification and documentation.
• Communicating effectively with internal development teams, providing technical insights and feedback throughout the design process.
• Participating in design reviews, troubleshooting, and optimization activities to ensure robust and scalable solutions.

Requirements:

• B.Tech/M.Tech degree in Electronics or Electrical Engineering.
• 2+ years of hands-on experience in CMOS circuit design, preferably with exposure to deep submicron process technologies.
• Proficiency in analog/mixed signal design methodologies and layout flows.
• Familiarity with JEDEC DDR interface requirements, DDR Timing, ODT, and SDRAM functionality is a strong plus.
• Basic understanding of ESD concepts and ASIC design flow.
• Demonstrated ability to execute assigned circuit design tasks with high quality and efficiency.
• Strong written and verbal communication skills for effective team interactions.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

Experience Level: Senior Employment Type: Full-time Workplace Type: Onsite Category: Engineering Industry: Technology Salary Range: Not stated Salary Min: Not stated Salary Max: Not stated Salary Currency: USD Salary Period: Year Required Skills: CMOS circuit design, analog/mixed signal design methodologies, layout flows, JEDEC DDR interface requirements, DDR Timing, ODT, SDRAM functionality, ESD concepts, ASIC design flow Preferred Skills: Not stated

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Honda has a clear vision for the future, and it’s a joyful one. We are looking for individuals with the skills, courage, persistence, and dreams that will help us reach our future-focused goals. At our core is innovation. Honda is constantly innovating and developing solutions to drive our business with record success. We strive to be a company that serves as a source of “power” that supports people around the world who are trying to do things based on their own initiative and that helps people expand their own potential. To this end, Honda strives to realize “the joy and freedom of mobility” by developing new technologies and an innovative approach to achieve a “zero environmental footprint.”

We are looking for qualified individuals with diverse backgrounds, experiences, continuous improvement values, and a strong work ethic to join our team.

Job Purpose: The Service Technical IT Applications unit is seeking a highly motivated, team-oriented, and customer-focused Technical Program Manager. This leadership role encompasses responsibility for overseeing programs and portfolio comprising of numerous critical applications. This position involves providing delivery and technical leadership and guiding the delivery team to ensure alignment with unit, department, divisional, and AHM business unit objectives. The Team Manager will oversee multiple projects, including business transformation initiatives utilizing modern technology and SaaS platforms for the Service division and working with global teams.

Key Accountabilities:

• Vision & Strategy:

Lead the IT team to support the Service and Planning business unit with their business application needs.

• Build and maintain high performing IT teams:

Foster associate development and long-term capability by teaching, coaching and mentoring, integrated with consistent and effective individual performance Management

• Achieve the project goals for the Team:

As approved annually, including schedule, budget and quality commitments

• Provide Technical and Solution Leadership:

Design business and technical solutions and provide solution architecture oversight.

• Promote IT and its capabilities:

Build NA relationships and network to achieve trust and credibility, by discovering and meeting the needs of internal and external customers

Qualifications, Experience, and Skills:

• IT / Computer Science related Bachelor Degree and/or equivalent work experience
• 8 or more years in Information Technology/Information Services
• 5 or more years supervisory, resource management, vendor management experience
• 5 or more years experience supporting IT Delivery, preferably in automotive industry
• 5 or more years experience managing and delivering large/ multiple projects, platforms, and products
• Must have strong project management skills to manage deadlines while delivering quality results, on time, on budget
• Experience managing teams with differing priorities and levels of expertise;
• Strong written and presentation skills and ability to effectively communicate at all levels of the organization
• Strong problem-solving and root cause analysis skills
• Working experience with estimation, planning, developing and managing a budget,
• People management, team building, coaching, mentoring, development, negotiations, conflict resolution, and strong interpersonal skills.
• Strong experience in vendor management, contracts management, SOW, RFP & RFQ process
• In-depth demonstrable knowledge of applicable SOX, PII, data privacy practices, security, and governance
• Experience leading multiple software development and implementation teams (Microsoft, Salesforce, Enterprise software etc)
• Experience in designing solutions and providing technical architecture oversight
• Experience as a leader for solution and business architecture, provide direction and oversight of design, methodologies, tooling, partnerships, and support models.
• Experience in performing modeling, gap analysis, and crafting architecture artifacts, such as context diagrams, data flow diagrams, business capability roadmaps.
• Experience in working with Architecture Review Board.
• Experience in leading the technical workstream for critical projects

Workstyle:

• Onsite at least 4 days per workweek. 1 remote workday a week may be possible with prior departmental approval.

Visa sponsorship issues:

• This position is not eligible for any work visa sponsorship.

Relocation assistance:

• Not eligible

What differentiates Honda and make us an employer of choice?

Total Rewards:

• Competitive Base Salary (pay will be based on several variables that include, but not limited to geographic location, work experience, etc.)
• Regional Bonus (when applicable)
• Manager Lease Car Program (No Cost - Car, Maintenance, and Insurance included)
• Industry-leading Benefit Plans (Medical, Dental, Vision, Rx)
• Paid time off, including vacation, holidays, shutdown
• Company Paid Short-Term and Long-Term Disability
• 401(K) Plan with company match + additional contribution

Career Growth:

• Advancement Opportunities
• Career Mobility
• Education Reimbursement for Continued Learning
• Training and Development Programs

Additional Offerings:

• Lifestyle Account
• Childcare Reimbursement Account
• Elder Care Support
• Tuition Assistance & Student Loan Repayment
• Wellbeing Program
• Community Service and Engagement Programs
• Product Programs

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Key responsibilities include:

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Back end P&R tools (Fusion Compiler, ICC2, Innovus)
• Excellent verbal and written presentation/communication skills are mandatory.

Requirements include:

• BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.
• Tool knowledge: front end Synthesis and back end PnR tools (Fusion Compiler, ICC2, Design Compiler, Genus),
• Tool knowledge: STA (Primetime, Tempus)

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

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The role involves leading the complete subsystem lifecycle,from requirements gathering and architecture definition to final release phases. This includes crafting subsystem architectures, developing comprehensive functional specifications, defining and implementing micro-architectures, and driving RTL quality checks.

The ideal candidate will have a minimum of 8 years of hands-on experience in RTL design and subsystem architecture for complex ASIC/SoC projects. They should be proficient with standard protocols including PCIe, DDR, UFS, USB, and AMBA, and have demonstrated expertise in low power design methodologies and DFT architecture.

As a leader, the candidate will inspire and guide their peers, leveraging their experience to drive innovation, efficiency, and reliability. They should be committed to continuous learning, open to new perspectives, and value an inclusive workplace where ideas from all backgrounds contribute to groundbreaking solutions.

The role offers a comprehensive range of health, wellness, and financial benefits to cater to the needs of the employee. The total rewards include both monetary and non-monetary offerings.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.

Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.
• Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.
• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.
• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.
• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.
• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.
• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

What You’ll Need:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimisation, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.
• Exposure to high-frequency design and low-power design methodologies.

Who You Are:

• Proactive, self-motivated, and driven to achieve technical excellence.
• Exceptional problem-solving and analytical skills with a keen attention to detail.
• Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.
• Collaborative team player who values knowledge sharing and mentoring others.
• Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.

The Team You’ll Be A Part Of:

You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

In addition to company holidays, we have ETO and FTO Programs.

• Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

• Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

You Are:

You are an accomplished engineering professional with a strong background in analog and mixed-signal circuit design. With over 12 years of industry experience, you have a deep understanding of circuit design fundamentals, device physics, and technology effects. You have successfully managed projects from specifications to silicon, and you are comfortable interfacing with both internal and external stakeholders. You are a proactive team player with excellent problem-solving skills and a knack for managing complex projects. Your high energy and flexible personality allow you to go the extra mile, fostering collaboration and driving projects to successful completion. You are adept at conflict resolution and possess strong customer-facing skills, making you an invaluable asset to any high-performing team.

What You’ll Be Doing:

Managing analog and mixed-signal IP projects from specifications to silicon. Interacting with customers to guide them and help adapt our solutions to their needs. Handling customer queries and debugging problems efficiently. Aligning with and improving established design processes. Interfacing with internal and external stakeholders to ensure high engagement levels. Collaborating with a global team to co-develop Analog Full Custom IPs such as GPIOs, I2C, I3C, SMBUS, eMMC, SVID, Quad SPI, JTAG, and more.

The Impact You Will Have:

Driving the integration of advanced capabilities into System on Chips (SoCs). Enabling customers to meet unique performance, power, and size requirements. Accelerating the time-to-market for differentiated products with reduced risk. Enhancing the design and development of high-performance silicon IP. Improving customer satisfaction through efficient problem-solving and support. Contributing to the continuous innovation and technological advancements at Synopsys.

What You’ll Need:

Bachelor's or Master's degree in Electrical Engineering or a related field from a reputed institution. 12+ years of industry experience in analog and mixed-signal circuit design. Proven experience in managing projects from specifications to silicon. Strong understanding of circuit design fundamentals, device physics, and technology effects. Proficiency in spice simulations and various sub-micron design methodologies.

Who You Are:

A proactive team player with strong written and verbal communication skills. High energy individual with the ability to go the extra mile. Creative and flexible personality with excellent customer-facing skills. Demonstrates good analysis and problem-solving skills. Adept at conflict resolution and fostering collaboration among team members.

The Team You’ll Be A Part Of:

You will be part of a strong development team specializing in GPIOs, Specialty IOs, and General Purpose Analog IPs. The team is distributed globally, bringing together experienced professionals from various sites. Together, you will co-develop high-performance analog full custom IPs and work on projects that push the boundaries of technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $266K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware team designs the custom silicon that powers the world’s most advanced AI systems. From system-level architecture to custom circuit implementations, we partner closely with model and infrastructure teams to deliver performance, power, and efficiency breakthroughs across all layers of the stack.

About the Role

We are seeking a highly skilled Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.

You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality.

In this role, you will:

• Develop, build and own tools, flows and methodologies for physical implementation
• Own physical implementation of floorplan blocks from floorplanning to final signoff
• Collaborate with RTL designers to drive optimal block implementation solutions
• Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners

Qualifications:

• BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
• Demonstrated success in taping out complex silicon designs
• Hands-on experience with block physical implementation and PPA convergence
• Strong coding experience with python, bazel, TCL
• Strong experience building physical design tools, flows and methodologies
• Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure.
• Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation

Bonus:

• Experience with AI or HPC-focused chips
• Experience with optimizing PPA for high performance compute cores
• Hands-on experience with top-level design methodologies

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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What you'll do

• The primary focus of the Physical Design Specialist (PDS) is to support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.
• In addition, PDS AEs will articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).

What you need

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Excellent verbal and written presentation/communication skills are mandatory.
• Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.

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What you'll do

• Providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.
• Diagnosing, troubleshooting, and resolving complex technical issues during customer installations and deployments.
• Training customers on new implementations, features, and capabilities of Synopsys RTL2GDS full flow solutions.

What you need

• Extensive experience with RTL to GDSII full flow and advanced node design methodologies.
• Hands-on proficiency with synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis.

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What you'll do

• Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.
• Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 9+ years of relevant experience.
• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).
• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes (like 2nm/3nm/5nm etc).
• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.
• Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.
• Outstanding verbal and written communication, presentation, and customer interaction skills.

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