{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/design-for-reliability"},"x-facet":{"type":"skill","slug":"design-for-reliability","display":"Design For Reliability","count":5},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cc76d9ba-dc2"},"title":"Staff Layout Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a passionate and detail-oriented engineer who thrives in the fast-paced world of advanced semiconductor layout. You possess a deep understanding of analog and mixed-signal CMOS design principles, with a particular focus on high-speed SerDes interfaces. Your expertise is backed by a solid academic foundation and practical experience, enabling you to tackle complex layout challenges with confidence.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Drive layout development for high-speed SerDes physical interfaces and complex analog/mixed-signal CMOS blocks.</li>\n</ul>\n<ul>\n<li>Lead the complete layout design process, including floorplanning, verification, and quality assurance, with a strong emphasis on reliability and manufacturability.</li>\n</ul>\n<ul>\n<li>Port designs across multiple foundry nodes, ensuring optimal performance and compliance with technology-specific requirements.</li>\n</ul>\n<ul>\n<li>Implement advanced techniques for signal integrity, ESD, and latch-up mitigation, such as differential routing, shielding, and biasing.</li>\n</ul>\n<ul>\n<li>Collaborate closely with design, verification, and manufacturing teams to deliver robust and scalable layout solutions.</li>\n</ul>\n<ul>\n<li>Utilize Synopsys EDA tools and scripting languages (TCL, Python) to automate layout tasks and optimize workflow efficiency.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enable Synopsys customers to achieve higher performance and reliability in their silicon designs.</li>\n</ul>\n<ul>\n<li>Accelerate the time-to-market for cutting-edge semiconductor products by delivering high-quality, manufacturable layouts.</li>\n</ul>\n<ul>\n<li>Enhance the robustness and scalability of Synopsys IP through meticulous attention to detail and innovative design solutions.</li>\n</ul>\n<ul>\n<li>Drive advancements in deep submicron CMOS technology adoption and integration.</li>\n</ul>\n<ul>\n<li>Foster a collaborative environment that supports knowledge sharing, mentorship, and professional growth.</li>\n</ul>\n<ul>\n<li>Support Synopsys’ leadership in chip design and verification by contributing to the development of industry-leading IP blocks.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>MSc in Electrical/Computer Engineering (or equivalent).</li>\n</ul>\n<ul>\n<li>Minimum 3 years hands-on experience in analog and mixed-signal CMOS layout, including high-speed SerDes interfaces.</li>\n</ul>\n<ul>\n<li>Deep knowledge of deep submicron CMOS technologies and design for reliability (EM/IR, matching, proximity effects).</li>\n</ul>\n<ul>\n<li>Proficiency in layout floorplanning, porting designs across foundry nodes, and implementing signal integrity and ESD mitigation strategies.</li>\n</ul>\n<ul>\n<li>Experience with custom digital and high-speed digital layout, as well as Synopsys EDA tools.</li>\n</ul>\n<ul>\n<li>Strong skills in UNIX environments, including shell scripting and command-line operations.</li>\n</ul>\n<ul>\n<li>Familiarity with scripting languages such as TCL and Python.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Excellent problem-solving, organizational, and communication skills.</li>\n</ul>\n<ul>\n<li>Self-motivated and proactive, with the ability to work independently and as part of a team.</li>\n</ul>\n<ul>\n<li>Effective collaborator who values diverse perspectives and fosters inclusive teamwork.</li>\n</ul>\n<ul>\n<li>Adaptable and open to new challenges, with a commitment to continuous improvement.</li>\n</ul>\n<ul>\n<li>Detail-oriented with a strong sense of ownership and pride in delivering high-quality work.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a dynamic, highly skilled team dedicated to developing world-class analog and mixed-signal IP for Synopsys’ global customer base. The team is focused on pushing the boundaries of high-speed interface design, reliability, and manufacturability, working together to solve complex challenges and deliver industry-leading solutions.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cc76d9ba-dc2","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/staff-layout-design-engineer/44408/93269033040","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["MSc in Electrical/Computer Engineering","Analog and mixed-signal CMOS layout","High-speed SerDes interfaces","Deep submicron CMOS technologies","Design for reliability","Layout floorplanning","Porting designs across foundry nodes","Signal integrity and ESD mitigation strategies","Custom digital and high-speed digital layout","Synopsys EDA tools","UNIX environments","Shell scripting and command-line operations","Scripting languages such as TCL and Python"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:06.360Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"MSc in Electrical/Computer Engineering, Analog and mixed-signal CMOS layout, High-speed SerDes interfaces, Deep submicron CMOS technologies, Design for reliability, Layout floorplanning, Porting designs across foundry nodes, Signal integrity and ESD mitigation strategies, Custom digital and high-speed digital layout, Synopsys EDA tools, UNIX environments, Shell scripting and command-line operations, Scripting languages such as TCL and Python"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_0b3b891d-187"},"title":"Analog Design, Principal Engineer","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are an experienced Analog Design Manager with a passion for high-speed SerDes technology. You have a proven track record in leading teams to develop cutting-edge analog integrated circuits. Your expertise in Multi-Gbps NRZ &amp; PAM4 SERDES IP, combined with your strong leadership skills, enables you to guide a team through complex design challenges. You thrive in a collaborative environment, working alongside analog and digital designers from diverse backgrounds. Your technical proficiency is complemented by your ability to develop schedules and action plans that ensure project success. With excellent communication and documentation skills, you effectively present design activities and solutions to critical issues. You are committed to fostering an environment of continuous improvement and operational excellence.</p>\n<p>What You’ll Be Doing:</p>\n<p>Directing and guiding the activities of a team of analog designers developing high-speed SERDES IP.\nConducting design reviews and evaluating the final results of simulation and electrical characterization reports.\nPresenting the results of design activities, technology assessments, or critical issue investigations and making recommendations for actions necessary to achieve desired results.\nSelecting, developing, and evaluating personnel to ensure the efficient operation of the team.\nDeveloping schedules and action plans to meet overall project timelines.\nReviewing documented design features and test plans.\nEnsuring that the team follows processes and operational policies for maximum design quality.\nConsulting on the electrical characterization of the SerDes IP product and proposing solutions for post-silicon design updates.</p>\n<p>What You’ll Need:</p>\n<p>B.Tech/BE/M.Tech/MS in Electronics Engineering.\n8+ years of experience in Analog Design for High-Speed SerDes applications.\n3-5 years of experience in a management or supervisory role.\nIn-depth familiarity with transistor level circuit design and sound CMOS design fundamentals.\nDetailed design experience with SerDes sub-circuits such as receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers,voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, and DAC, DSP, Signal Integrity\nFamiliarity with both analog and digital circuits and issues related to interfacing and timing between them.\nAware of ESD issues (i.e. circuit techniques, layout).\nFamiliarity with custom digital design (i.e. highspeed logic paths).\nKnowledge of design for reliability (i.e. EM, IR, aging, etc.).\nKnowledge of layout effects (i.e. matching, reliability, proximity effects, etc.).\nGood communication and documentation skills.</p>\n<p>The Impact You Will Have:</p>\n<p>Driving the development of high-speed SerDes IP that meets industry standards and customer requirements.\nFostering innovation and excellence within the analog design team.\nEnsuring the delivery of high-quality, reliable analog integrated circuits.\nContributing to the advancement of Synopsys&#39; technology portfolio in the analog and mixed-signal domains.\nEnhancing the performance and efficiency of our high-speed communication products.\nSupporting the growth and development of team members through effective leadership and mentorship.</p>\n<p>Who You Are:</p>\n<p>You are a proactive leader with a strong technical background in analog design. You possess excellent problem-solving skills and the ability to make sound decisions under pressure. Your collaborative nature allows you to work effectively with cross-functional teams. You are detail-oriented and have a keen eye for quality. Your passion for continuous learning and improvement drives you to stay updated with the latest industry trends and technologies. You are committed to fostering a positive and inclusive team culture, encouraging innovation and excellence.</p>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will be part of a fast-growing analog and mixed-signal R&amp;D team developing high-speed analog integrated circuits in the latest FinFET process nodes. The team is composed of talented analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_0b3b891d-187","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/mississauga/analog-design-principal-engineer-14131/44408/91386421616","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Analog Design","High-Speed SerDes Technology","Multi-Gbps NRZ & PAM4 SERDES IP","Transistor Level Circuit Design","CMOS Design Fundamentals","SerDes Sub-Circuits","ESD Issues","Custom Digital Design","Design for Reliability","Layout Effects"],"x-skills-preferred":["Leadership","Communication","Documentation","Problem-Solving","Decision-Making","Collaboration","Quality Assurance","Continuous Learning","Innovation","Excellence"],"datePosted":"2026-04-05T13:18:01.010Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mississauga"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Analog Design, High-Speed SerDes Technology, Multi-Gbps NRZ & PAM4 SERDES IP, Transistor Level Circuit Design, CMOS Design Fundamentals, SerDes Sub-Circuits, ESD Issues, Custom Digital Design, Design for Reliability, Layout Effects, Leadership, Communication, Documentation, Problem-Solving, Decision-Making, Collaboration, Quality Assurance, Continuous Learning, Innovation, Excellence"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5f4e85a9-296"},"title":"Staff Analog Design Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15391</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/23/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ &amp; PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.</p>\n<p>You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.</p>\n<p>Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.</li>\n</ul>\n<ul>\n<li>Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.</li>\n</ul>\n<ul>\n<li>Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.</li>\n</ul>\n<ul>\n<li>Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.</li>\n</ul>\n<ul>\n<li>Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.</li>\n</ul>\n<ul>\n<li>Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.</li>\n</ul>\n<ul>\n<li>Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.</li>\n</ul>\n<ul>\n<li>Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.</li>\n</ul>\n<ul>\n<li>Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.</li>\n</ul>\n<ul>\n<li>Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.</li>\n</ul>\n<ul>\n<li>Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.</li>\n</ul>\n<ul>\n<li>Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).</li>\n</ul>\n<ul>\n<li>Proven expertise with FinFET technologies and CMOS tape-outs.</li>\n</ul>\n<ul>\n<li>Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.</li>\n</ul>\n<ul>\n<li>Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).</li>\n</ul>\n<ul>\n<li>Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.</li>\n</ul>\n<ul>\n<li>Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).</li>\n</ul>\n<ul>\n<li>Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.</li>\n</ul>\n<ul>\n<li>Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.</li>\n</ul>\n<ul>\n<li>Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).</li>\n</ul>\n<ul>\n<li>Excellent communication and documentation skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative and open-minded, eager to share knowledge and learn from others.</li>\n</ul>\n<ul>\n<li>Detail-oriented and thorough, with a commitment to delivering high-quality results.</li>\n</ul>\n<ul>\n<li>Analytical thinker with strong problem-solving abilities and a proactive approach.</li>\n</ul>\n<ul>\n<li>Excellent communicator, able to convey complex technical concepts clearly.</li>\n</ul>\n<ul>\n<li>Adaptable and resilient in fast-paced, dynamic environments.</li>\n</ul>\n<ul>\n<li>Committed to fostering an inclusive, innovative, and supportive workplace.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a world-class analog and mixed-signal R&amp;D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>What is it like to be an Analog Design Engineer at Synopsys?</p>\n<p>Arman Shahmuradyan</p>\n<p>Analog Design, Manager</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and patern</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5f4e85a9-296","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/staff-analog-design-engineer/44408/92076328848","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog IC design","FinFET technologies","CMOS tape-outs","Multi-Gbps high-speed designs","SERDES architectures","analog/digital co-design","calibration","adaptation","timing handoff","ESD protection","custom digital design","design for reliability","schematic entry","physical layout","design verification tools","SPICE simulators","scripting languages","system-level budgeting","signal integrity"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:05:32.632Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad, Telangana, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog IC design, FinFET technologies, CMOS tape-outs, Multi-Gbps high-speed designs, SERDES architectures, analog/digital co-design, calibration, adaptation, timing handoff, ESD protection, custom digital design, design for reliability, schematic entry, physical layout, design verification tools, SPICE simulators, scripting languages, system-level budgeting, signal integrity"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8fec4f8e-c82"},"title":"Product Quality Engineer","description":"<p><strong>Compensation</strong></p>\n<p>Hardware $123K – $285K • Offers Equity</p>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team</strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong>About the Role</strong></p>\n<p>We’re looking for a product quality engineer, who will be responsible for driving technical initiatives related to the quality and reliability of our AI supercomputer hardware systems to ensure product success from concept to launch and through mass production. You’ll have the opportunity to work with a wide range of stakeholders, from design engineering and operations teams, TPMs, external industry vendors and partners to ensure that all products are developed and delivered on time and to the highest quality standards.</p>\n<p>This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong>In this role, you will:</strong></p>\n<ul>\n<li>In this role, you’ll be responsible for defining product quality and reliability targets and driving initiatives to ensure product success from concept to launch.</li>\n</ul>\n<ul>\n<li>Lead and develop the overall product quality and reliability strategy and process for next-gen AI hardware system development, you will have the opportunity to work with a wide range of stakeholders, from design engineering and operations teams, TPMs and external industry vendors and partners to ensure that all products are developed and delivered on time and to the highest quality standards.</li>\n</ul>\n<ul>\n<li>Lead the team to establish NPI product quality control process, define reliability qualification strategy, define clear milestones and deliverables, drive internal process improvements across multiple terms and functions.</li>\n</ul>\n<ul>\n<li>Drive the design and execution of comprehensive quality and reliability assurance plans, testing protocols, and validation processes to ensure all hardware systems meet stringent performance, reliability and compliance standards.</li>\n</ul>\n<ul>\n<li>Champion the use of advanced data analytics and statistical methods for analysis and monitoring of key quality metrics (e.g., yield, defect rates, MTBF) to monitor performance, predict potential failures, and guide product improvements.</li>\n</ul>\n<ul>\n<li>Lead failure analysis, root cause identification, and corrective actions for system failures in both development and operational environments.</li>\n</ul>\n<ul>\n<li>Collaborate with suppliers to ensure that all sub-components meet quality standards and performance specifications.</li>\n</ul>\n<ul>\n<li>Visit vendors&#39; facilities and review their manufacturing environment to assess and improve their procedures.</li>\n</ul>\n<ul>\n<li>Lead component supplier and JDM/CM quality control audits and performance reviews to ensure component and system reliability.</li>\n</ul>\n<ul>\n<li>Own overall product quality process development of the hardware product. This includes the PCB, PCBA, cabling and connector, chassis, rack, power, and cooling components, subsystems spanning internal and external development work through successful deployment into the infrastructure and support of production workloads at scale.</li>\n</ul>\n<ul>\n<li>Develop and manage overall product quality requirements, scope, schedules, and deliverables with engineering teams, TPMs, partners and key stakeholders.</li>\n</ul>\n<ul>\n<li>Communicate effectively with cross-functional teams to ensure successful execution of programs.</li>\n</ul>\n<ul>\n<li>Utilize problem-solving skills to resolve issues and overcome obstacles, perform risk assessment, risk mitigation and change management on projects.</li>\n</ul>\n<ul>\n<li>Manage multiple projects simultaneously.</li>\n</ul>\n<ul>\n<li>Monitor project progress and ensure deadlines and standards are met.</li>\n</ul>\n<p><strong>You might thrive in this role if you:</strong></p>\n<ul>\n<li>Have an impressive track record of leading complex projects from concept to production launch and have the ability to work with cross-functional teams to ensure successful execution of programs.</li>\n</ul>\n<ul>\n<li>Are a creative, detail-oriented, and self-motivated individual looking for an exciting opportunity in the tech industry, this could be the perfect role for you</li>\n</ul>\n<ul>\n<li>Stay up to date on industry trends and product quality engineering of high-performance computing systems.</li>\n</ul>\n<ul>\n<li>Like being a close partner with cross-functional teams to understand key design changes requiring validation to accurately integrate engineering validation needs into the overall system build.</li>\n</ul>\n<ul>\n<li>Have experience driving development timelines for new platform introduction and managing internal review processes.</li>\n</ul>\n<ul>\n<li>Have significant experience driving creativity, quality, reliability, and schedule at multinational JDM/CM vendors.</li>\n</ul>\n<ul>\n<li>Are deeply familiar with mechanical and electrical Design For Quality (DFQ), Excellence (DFX), Manufacturability (DFM), Assembly (DFA), Test (DFT), and Design for Reliability (DFR), etc.</li>\n</ul>\n<ul>\n<li>Have experience with 8D and various troubleshooting/root cause analysis methodology such as 5 Whys, Fishbones, etc..</li>\n</ul>\n<ul>\n<li>Are excited by capturing, analyzing, and presenting key quality metrics data.</li>\n</ul>\n<ul>\n<li>Are keen on root cause corrective actions.</li>\n</ul>\n<ul>\n<li>Are comfortable with ambiguity and rapidly changing conditions.</li>\n</ul>\n<p>_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.</p>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8fec4f8e-c82","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/b45827df-e1f6-4c91-a78e-80c3669ec6e4","x-work-arrangement":"Hybrid","x-experience-level":"senior","x-job-type":"Full time","x-salary-range":"Hardware $123K – $285K • Offers Equity","x-skills-required":["product quality","reliability","quality assurance","testing protocols","validation processes","data analytics","statistical methods","failure analysis","root cause identification","corrective actions","supplier collaboration","quality control audits","performance reviews","project management","problem-solving","risk assessment","risk mitigation","change management"],"x-skills-preferred":["mechanical and electrical Design For Quality (DFQ)","Excellence (DFX)","Manufacturability (DFM)","Assembly (DFA)","Test (DFT)","Design for Reliability (DFR)","8D","5 Whys","Fishbones"],"datePosted":"2026-03-08T22:17:17.187Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"product quality, reliability, quality assurance, testing protocols, validation processes, data analytics, statistical methods, failure analysis, root cause identification, corrective actions, supplier collaboration, quality control audits, performance reviews, project management, problem-solving, risk assessment, risk mitigation, change management, mechanical and electrical Design For Quality (DFQ), Excellence (DFX), Manufacturability (DFM), Assembly (DFA), Test (DFT), Design for Reliability (DFR), 8D, 5 Whys, Fishbones","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":123000,"maxValue":285000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_83f45538-d2c"},"title":"Analog Design, Sr Staff Engineer","description":"<p>Opening. This role is responsible for driving innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions. The successful candidate will be a seasoned analog design professional with a passion for pushing technology boundaries.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Review SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.</p>\n<p>Investigate and architect circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.</p>\n<p>Collaborate with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.</p>\n<p>Oversee and guide the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.</p>\n<p>Present and review simulation data with internal teams and external stakeholders, including industry panels and customer reviews.</p>\n<p>Document design features, test plans, and results, and consult on electrical characterization and post-silicon analysis for product enhancements.</p>\n<p>Analyze customer silicon data to identify design improvement opportunities and propose solutions for post-silicon updates.</p>\n<p><strong>What you need</strong></p>\n<p>MTech/MS with 7+ years or BTech/BS with 8+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).</p>\n<p>Proven expertise with FinFET technologies and CMOS tape-outs.</p>\n<p>Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.</p>\n<p>Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).</p>\n<p>Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.</p>\n<p>Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).</p>\n<p>Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.</p>\n<p>Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.</p>\n<p>Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).</p>\n<p>Excellent communication and documentation skills.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_83f45538-d2c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/analog-design-sr-staff-engineer/44408/91089467936","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog IC design","FinFET technologies","CMOS tape-outs","Multi-Gbps high-speed designs","SERDES architectures","SERDES sub-circuits","analog/digital co-design","calibration","adaptation","timing handoff","ESD protection","custom digital design","design for reliability"],"x-skills-preferred":["scripting languages","schematic entry","physical layout","design verification tools","SPICE simulators"],"datePosted":"2026-01-28T15:10:19.833Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog IC design, FinFET technologies, CMOS tape-outs, Multi-Gbps high-speed designs, SERDES architectures, SERDES sub-circuits, analog/digital co-design, calibration, adaptation, timing handoff, ESD protection, custom digital design, design for reliability, scripting languages, schematic entry, physical layout, design verification tools, SPICE simulators"}]}