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You will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.</p>\n<p>Your responsibilities will include:</p>\n<ul>\n<li>Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.</li>\n<li>Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.</li>\n<li>Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.</li>\n<li>Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.</li>\n<li>Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.</li>\n<li>Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.</li>\n<li>Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys&#39; technical edge.</li>\n</ul>\n<p>You will accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. 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You will strengthen Synopsys&#39; reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.</p>\n<p>To be successful in this role, you will need:</p>\n<ul>\n<li>B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.</li>\n<li>5-8 years of hands-on experience in the Physical Verification (PV) domain.</li>\n<li>Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.</li>\n<li>Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.</li>\n<li>Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.</li>\n<li>Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.</li>\n<li>Exposure to competitive EDA tools and awareness of their strengths and limitations.</li>\n</ul>\n<p>You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. 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This is a visible, cross-functional role that requires strong technical depth, execution excellence, and stakeholder management skills.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Collaborate closely with cross-functional teams (R&amp;D, Product Management, Sales, and Pre-Sales) to ensure end-to-end product success</li>\n<li>Define, develop, and execute product engineering strategies aligned with business and customer objectives</li>\n<li>Act as the primary technical interface between internal engineering teams and external stakeholders</li>\n<li>Partner with Sales and Pre-Sales teams to provide technical inputs, customer insights, and execution support</li>\n<li>Build, manage, and track detailed project time plans and schedules across multiple initiatives</li>\n<li>Drive execution rigor, issue prioritization, and risk mitigation across concurrent projects</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum 8 years of experience in VLSI product engineering</li>\n<li>Strong exposure to analog and digital SoC design flows and methodologies</li>\n<li>Prior hands-on experience in one or more of the following is preferred:<ul>\n<li>RTL Development</li>\n<li>RTL Verification</li>\n<li>RTL-to-GDS flow</li>\n</ul>\n</li>\n<li>Proven track record of working across multiple technology nodes and driving product innovation</li>\n<li>Strong customer-centric mindset with the ability to multitask, prioritize effectively, and manage multiple complex projects</li>\n<li>Demonstrated experience communicating and influencing across multiple levels of the organization, including senior leadership</li>\n<li>Good understanding of database management, data quality, and data cleanliness across the product portfolio</li>\n<li>Excellent written and verbal communication skills</li>\n</ul>\n<p>Nice to Have:</p>\n<ul>\n<li>Experience with VLSI design automation tools and methodologies</li>\n<li>Awareness of industry trends and emerging technologies in VLSI</li>\n<li>Certification in Product Management, Project Management, or a related discipline</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a1fbe166-d22","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/project-engineering-management-staff-engineer/44408/93189758032","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL Development","RTL Verification","RTL-to-GDS flow","analog and digital SoC design flows and methodologies","database management","data quality","data cleanliness"],"x-skills-preferred":["VLSI design automation tools and methodologies","industry trends and emerging technologies in VLSI","Product Management","Project Management"],"datePosted":"2026-04-05T13:20:28.647Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL Development, RTL Verification, RTL-to-GDS flow, analog and digital SoC design flows and methodologies, database management, data quality, data cleanliness, VLSI design automation tools and methodologies, industry trends and emerging technologies in VLSI, Product Management, Project Management"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e9f309b8-35d"},"title":"Senior Manager, ASIC Digital Design","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Senior Manager, ASIC Digital Design, you will lead a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions. You will collaborate with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Leading a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions</li>\n<li>Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products</li>\n<li>Planning, scheduling, and driving all phases of SERDES PHY IP design, from specification through productization and customer support</li>\n<li>Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles</li>\n<li>Mentoring and developing team members, fostering technical growth, and a culture of innovation</li>\n<li>Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges</li>\n</ul>\n<p>The impact you will have includes delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency, empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications, and driving technical innovation that strengthens Synopsys&#39; leadership in the mixed-signal IP market.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e9f309b8-35d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/kanata/senior-manager-asic-digital-design/44408/93286401664","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verilog","System Verilog","front-end design flows","linting","synthesis","static timing analysis","cross-domain clocking","DFT","power optimization"],"x-skills-preferred":["DDR memory","DDR PHY architecture"],"datePosted":"2026-04-05T13:20:15.775Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Kanata"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verilog, System Verilog, front-end design flows, linting, synthesis, static timing analysis, cross-domain clocking, DFT, power optimization, DDR memory, DDR PHY architecture"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_de89b568-8b1"},"title":"ASIC Digital Design, Sr Manager","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking a visionary technical leader with a great passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and SystemVerilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams - architecture, verification, physical implementation, and firmware - to deliver industry-leading SecurityIP solutions.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Leading a diverse team of design engineers in the development of next-generation SecurityIP solutions.</li>\n<li>Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.</li>\n<li>Driving all phases of SecurityIP design, from specification through productization and customer support.</li>\n<li>Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.</li>\n<li>Mentoring and developing team members, fostering technical growth and a culture of innovation.</li>\n<li>Engaging with customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.</li>\n</ul>\n<p><strong>Impact</strong></p>\n<ul>\n<li>Delivering industry-leading SecurityIP solutions that set new benchmarks for speed, bandwidth, and efficiency.</li>\n<li>Empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications.</li>\n<li>Driving technical innovation that strengthens Synopsys’ leadership in the mixed-signal IP market.</li>\n<li>Mentoring and growing a world-class engineering team, ensuring continued excellence and market relevance.</li>\n<li>Enhancing product quality and reliability through rigorous design and verification processes.</li>\n<li>Facilitating successful customer adoption and satisfaction through expert support and problem-solving.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor’s degree or higher in Electrical Engineering, with 12-15 years of complex technical development experience.</li>\n<li>Minimum 2 years’ experience in people management and employee development.</li>\n<li>Proficiency in synthesizable Verilog and SystemVerilog design concepts and implementation.</li>\n<li>Strong background in front-end design flows: linting, synthesis, static timing analysis (STA), cross-domain clocking, DFT, and power optimization.</li>\n<li>Excellent communication skills and the ability to work independently and collaboratively.</li>\n<li>Understanding of SecurityIP architecture is a plus.</li>\n</ul>\n<p><strong>Team</strong></p>\n<p>You’ll join the Synopsys SecurityIP team - a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_de89b568-8b1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/asic-digital-design-sr-manager/44408/93375604608","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["synthesizable Verilog","SystemVerilog","linting","synthesis","static timing analysis","power optimization","front-end design flows","SecurityIP architecture"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:19:34.586Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"synthesizable Verilog, SystemVerilog, linting, synthesis, static timing analysis, power optimization, front-end design flows, SecurityIP architecture"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_0240a284-beb"},"title":"Senior Manager of Customer Program Management (Strategic Engagements)","description":"<p><strong>Job Summary</strong></p>\n<p>We are seeking a senior manager of customer program management to lead a team of program managers supporting IP engagements and customer success. The ideal candidate will have deep expertise in program management, hands-on experience managing SoC design flows, and the IP ecosystem.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Lead a team of program managers supporting IP engagements and customer success</li>\n<li>Shape the strategic direction of customer experience for your region</li>\n<li>Drive end-to-end customer journeys from pre-sales through silicon success</li>\n<li>Collaborate with cross-functional teams to ensure customer satisfaction</li>\n<li>Manage escalations and resolve issues proactively</li>\n<li>Partner with sales to support contract closure</li>\n</ul>\n<p><strong>Impact</strong></p>\n<ul>\n<li>Enhance customer satisfaction and IP integration success</li>\n<li>Improve Synopsys products through customer feedback</li>\n<li>Resolve escalations efficiently to maintain strong relationships</li>\n<li>Lead and inspire a high-performing team</li>\n<li>Drive operational excellence and strategic improvements</li>\n<li>Support key business and customer objectives</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>B.S./M.S. in Electrical Engineering or related field</li>\n<li>Experience working with SoC design flows and the IP IC Design ecosystem</li>\n<li>15+ years in engineering or program management roles</li>\n<li>10+ years of people management experience</li>\n<li>Experience with contract negotiations</li>\n<li>Strong communication and leadership skills</li>\n</ul>\n<p><strong>Who We Are Looking For</strong></p>\n<ul>\n<li>Strategic, customer-centric, and agile</li>\n<li>Collaborative and inspirational leader</li>\n<li>Excellent communicator and problem solver</li>\n</ul>\n<p><strong>The Team You&#39;ll Be A Part Of</strong></p>\n<p>Join the Customer Engagement and Success team, working with global partners and cross-functional Synopsys groups to deliver IP integration and customer satisfaction.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_0240a284-beb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/senior-manager-of-customer-program-management-strategic-engagements/44408/93550761328","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$198000-$297000","x-skills-required":["SoC design flows","IP IC Design ecosystem","program management","customer success","contract negotiations","communication","leadership"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:15:42.525Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"occupationalCategory":"General Management","industry":"Technology","skills":"SoC design flows, IP IC Design ecosystem, program management, customer success, contract negotiations, communication, leadership","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":198000,"maxValue":297000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f19bcb42-6b9"},"title":"DPF 2026 Internship AI integration","description":"<p>Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with passionate teams globally. Explore your interests, share your ideas, and bring them to life while shaping your career path within our inclusive culture that fosters innovation and collaboration.</p>\n<p>At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide - and having fun in the process! You&#39;ll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path.</p>\n<p>**Internship Experience:* Audit existing AI tool integrations in DPF development workflows, including code generation, review, testing, and documentation. The DPF (Data Processing Framework) team develops and maintains a framework for post-processing simulation data. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.</p>\n<p><strong>Responsibilities</strong></p>\n<p>Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.</p>\n<p>Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.</p>\n<p>Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.</p>\n<p>Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.</p>\n<p>Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&amp;R-aware synthesis using tools such as Fusion Compiler.</p>\n<p>Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.</p>\n<p>Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.</p>\n<p><strong>Requirements</strong></p>\n<p>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.</p>\n<p>4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.</p>\n<p>Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.</p>\n<p>Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.</p>\n<p>Familiarity with high-speed design (&gt;600MHz), P&amp;R-aware synthesis, and EDA tools such as Fusion Compiler.</p>\n<p>Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.</p>\n<p>Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).</p>\n<p>Exposure to quality processes in IP design and verification is an advantage.</p>\n<p>Prior experience as a technical lead or mentor is highly desirable.</p>\n<p><strong>Who We Are Looking For</strong></p>\n<p>Innovative thinker with a solutions-oriented mindset and a passion for technology.</p>\n<p>Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.</p>\n<p>Natural leader with mentoring abilities, fostering inclusion and diversity within the team.</p>\n<p>Detail-oriented professional with strong analytical and problem-solving skills.</p>\n<p>Self-motivated, adaptable, and eager to drive technical excellence and process improvements.</p>\n<p>Committed to continuous learning and staying ahead of industry trends.</p>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>You will join the R&amp;D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_02d8b8e9-445","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/staff-asic-rtl-design-engineer/44408/92577687840","x-work-arrangement":"Onsite","x-experience-level":"Staff","x-job-type":"Full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design","Verilog/SystemVerilog","Simulation tools","Design flows","Linting","Static timing analysis","Formal checking","P&R-aware synthesis","Fusion Compiler","Version control systems","Scripting languages","Industry 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work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology.</p>\n<p>With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes.</p>\n<p>You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus.</p>\n<p>Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.</p>\n<p>You are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements.</p>\n<p>As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment.</p>\n<p>Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions.</p>\n<p>You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.</p>\n<p>Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.</p>\n<p>Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.</p>\n<p>Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.</p>\n<p>Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.</p>\n<p>Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.</p>\n<p>Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.</p>\n<p>Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.</p>\n<p>Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses.</p>\n<p>Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market.</p>\n<p>Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps.</p>\n<p>Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges.</p>\n<p>Contribute to the development of next-generation verification methodologies and best practices within Synopsys.</p>\n<p>Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.</p>\n<p>B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.</p>\n<p>5-8 years of hands-on experience in the Physical Verification (PV) domain.</p>\n<p>Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.</p>\n<p>Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.</p>\n<p>Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.</p>\n<p>Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.</p>\n<p>Exposure to competitive EDA tools and awareness of their strengths and limitations.</p>\n<p>An analytical thinker with strong problem-solving abilities and meticulous attention to detail.</p>\n<p>A collaborative team player who fosters knowledge sharing and mentorship.</p>\n<p>Effective communicator, capable of translating technical concepts to diverse audiences.</p>\n<p>Adaptable and proactive, with a passion for continuous learning and innovation.</p>\n<p>Customer-focused, with a commitment to delivering high-quality solutions on time.</p>\n<p>Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.</p>\n<p>Join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design.</p>\n<p>Work closely with foundry partners, internal R&amp;D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.</p>\n<p>Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_876cc8c0-1dd","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/application-engineering-staff-engineer-icv-runset-development/44408/92577688192","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Physical Verification","EDA tools","Perl","Tcl","Python","CMOS layout","ASIC design flows","foundry process requirements"],"x-skills-preferred":[],"datePosted":"2026-03-10T12:10:31.325Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Verification, EDA tools, Perl, Tcl, Python, CMOS layout, ASIC design flows, foundry process requirements"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b5f1283c-76e"},"title":"ASIC Digital Design, Sr Staff/Principal Engineer - DDR","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Date posted</strong>: 03/09/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect.</p>\n<p>Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.</p>\n<p>You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.</p>\n<p>With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.</p>\n<p>Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Lead and Drive all aspects of complete IP Design execution from start to end.</li>\n</ul>\n<ul>\n<li>Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.</li>\n</ul>\n<ul>\n<li>Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.</li>\n</ul>\n<ul>\n<li>Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.</li>\n</ul>\n<ul>\n<li>Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.</li>\n</ul>\n<ul>\n<li>Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.</li>\n</ul>\n<ul>\n<li>Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.</li>\n</ul>\n<ul>\n<li>Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.</li>\n</ul>\n<ul>\n<li>Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.</li>\n</ul>\n<ul>\n<li>Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.</li>\n</ul>\n<ul>\n<li>Enabling customers to achieve faster time-to-market and superior silicon performance.</li>\n</ul>\n<ul>\n<li>Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.</li>\n</ul>\n<ul>\n<li>Driving continuous improvement in design methodologies, enhancing efficiency and product quality.</li>\n</ul>\n<ul>\n<li>Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.</li>\n</ul>\n<ul>\n<li>10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.</li>\n</ul>\n<ul>\n<li>Past experience of leading IP deign projects, team.</li>\n</ul>\n<ul>\n<li>In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.</li>\n</ul>\n<ul>\n<li>Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.</li>\n</ul>\n<ul>\n<li>Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).</li>\n</ul>\n<ul>\n<li>Familiarity with scripting languages such as Perl or Shell—an advantage.</li>\n</ul>\n<ul>\n<li>Demonstrated ability to technically lead or mentor small teams of engineers.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A collaborative team player who thrives in a multi-site, multicultural environment.</li>\n</ul>\n<ul>\n<li>An effective communicator, able to translate complex technical concepts for diverse audiences.</li>\n</ul>\n<ul>\n<li>A proactive problem-solver with strong analytical and troubleshooting skills.</li>\n</ul>\n<ul>\n<li>Self-motivated, showing high initiative and ownership of responsibilities.</li>\n</ul>\n<ul>\n<li>Adaptable and eager to learn, always seeking opportunities for personal and professional growth.</li>\n</ul>\n<ul>\n<li>Committed to fostering a positive, inclusive, and innovative team culture.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join the R&amp;D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.</p>\n<p>As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.</p>\n<p>The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.</p>\n<p>Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world.</p>\n<p>We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.</p>\n<p>We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b5f1283c-76e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-principal-engineer-ddr/44408/92599737760","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","System architecture","ASIC solutions","High-performance protocols","DDR PHY","PCIe","USB","HBM","Verilog","SystemVerilog","Simulation tools","Design flows","Lint","CDC","Synthesis","Static timing analysis","Formal verification","Control path-oriented designs","Asynchronous FIFOs","DMA","SPRAM/DPRAM interfaces","Scripting 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As a key member of our Security IP team, you will be responsible for designing and implementing secure ASIC solutions for various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>What You&#39;ll Be Doing:</strong></p>\n<ul>\n<li>Designing and implementing RTL in Verilog and/or System Verilog for Security Applications.</li>\n<li>Creating and designing test environments for digital hardware Security IP cores and subsystems using System Verilog and UVM.</li>\n<li>Conducting hardware verification of IP cores and subsystems utilizing modern verification techniques such as UVM or formal verification.</li>\n<li>Collaborating with hardware and software security experts to perform functional and performance analysis of embedded hardware/software IP solutions.</li>\n<li>Working within an international team setup, contributing to global projects.</li>\n<li>Ensuring adherence to high-quality standards and best practices in digital design and verification processes.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enhancing the performance and security of our IP cores and subsystems.</li>\n<li>Contributing to the rapid integration of advanced capabilities into SoCs, meeting unique performance, power, and size requirements.</li>\n<li>Reducing time-to-market for differentiated products with minimized risk.</li>\n<li>Driving innovation in the fields of CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive.</li>\n<li>Collaborating with a diverse team to deliver leading-edge solutions that shape the future of technology.</li>\n<li>Playing a key role in maintaining Synopsys&#39; position as a leader in chip design and software security.</li>\n</ul>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>3+ years Experience in RTL design of hardware IP components.</li>\n<li>Proficiency in ASIC verification using System Verilog, UVM, and or Verilog</li>\n<li>Ability to create detailed specifications for test environments.</li>\n<li>MSc or PhD in Electrical Engineering or Computer Science.</li>\n<li>Strong understanding of IC Design flows and exceptional problem-solving and debugging skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A strong communicator with excellent written and verbal skills.</li>\n<li>A team player who thrives in a collaborative international environment.</li>\n<li>An innovative thinker who is passionate about technology and continuous improvement.</li>\n<li>Detail-oriented and committed to delivering high-quality work.</li>\n<li>Adaptable and able to manage multiple tasks effectively.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will be joining the Security IP team in Eindhoven at the High Tech Campus, a dynamic and innovative group dedicated to extending the Security IP business in markets such as CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive. Our team is composed of experts in hardware and software security, working together to develop state-of-the-art IP cores and subsystems. We value collaboration, creativity, and a commitment to excellence.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_3a6efc4b-131","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/eindhoven/asic-security-staff-engineer/44408/91940192192","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","Verilog","System Verilog","UVM","Formal verification","IC Design flows","Problem-solving and debugging skills"],"x-skills-preferred":["ASIC verification","Digital hardware Security IP cores and subsystems","Embedded hardware/software IP solutions"],"datePosted":"2026-03-09T11:09:25.644Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Eindhoven"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, Verilog, System Verilog, UVM, Formal verification, IC Design flows, Problem-solving and debugging skills, ASIC verification, Digital hardware Security IP cores and subsystems, Embedded hardware/software IP solutions"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_942bad4c-0f8"},"title":"Applications Engineering, Sr Engineer (STA/ECO Engineer)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking a highly motivated engineering professional with a passion for solving complex technical challenges in the semiconductor domain. You will apply engineering expertise to support EDA product specifications and deployment for leading semiconductor design houses and foundries. You will engage directly with global customers, IP providers, and foundries to understand and address design challenges for cutting-edge SoCs and 3DICs.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Apply engineering expertise to support EDA product specifications and deployment for leading semiconductor design houses and foundries.</li>\n<li>Engage directly with global customers, IP providers, and foundries to understand and address design challenges for cutting-edge SoCs and 3DICs.</li>\n<li>Work closely with product development teams to influence the creation and evolution of state-of-the-art EDA products.</li>\n<li>Deploy and support Synopsys Seascape platform – the industry’s first and only true big-data design platform.</li>\n<li>Provide expert guidance and consultation to customers, solving STA, Power, Signal, and Reliability challenges across Chip-Package-System at advanced nodes.</li>\n<li>Own customer problems, engage proactively with selected accounts, and deliver comprehensive technical solutions throughout the sales opportunity lifecycle.</li>\n<li>Gather and analyze customer requirements to drive enhancements in Synopsys software, collaborating with product teams to translate needs into new product capabilities.</li>\n<li>Participate in internal corporate initiatives, sharing knowledge and creating best practices within and across disciplines.</li>\n<li>Develop EDA best practices, solutions, and FAQs for the knowledge base to support both internal and external stakeholders.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>At least 3+ years of experience in the semiconductor domain, with a strong background in STA analysis, ECO, timing closure, or PDN at block or SoC level.</li>\n<li>Proficiency in providing technical support for PDN and/or Timing Signoff domains, with proven ability to assist clients and resolve issues.</li>\n<li>Hands-on experience with industry-leading tools: PrimeTime, RHSC, PrimeClosure, PTECO, Tweaker.</li>\n<li>Knowledge of PDN implementation and semiconductor design flows is highly desirable.</li>\n<li>Strong programming skills to automate workflows and develop solutions for complex engineering challenges.</li>\n</ul>\n<p><strong>Team</strong></p>\n<p>You will join the Signoff Support Group, a dynamic team responsible for deploying and supporting Synopsys’ broad portfolio of design analysis and signoff solutions. The team’s core focus spans static timing analysis, advanced signal integrity, power and power integrity, parasitic extraction, ECO closure, transistor-level analysis, library characterization, and Multiphysics. You will collaborate with software developers, architects, and product engineers to drive the development and deployment of industry-leading products, contributing to Synopsys’ continued success in the semiconductor industry.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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You will work closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.</li>\n<li>Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.</li>\n<li>5-8 years of hands-on experience in the Physical Verification (PV) domain.</li>\n<li>Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.</li>\n<li>Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.</li>\n<li>Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.</li>\n<li>Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.</li>\n<li>Exposure to competitive EDA tools and awareness of their strengths and limitations.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_88aed163-18b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/application-engineering-staff-engineer-physical-verification-runset-development/44408/92048243536","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["EDA tools","Physical Verification","Scripting skills"],"x-skills-preferred":["CMOS layout","ASIC design flows","Foundry process requirements"],"datePosted":"2026-03-06T07:21:00.526Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"EDA tools, Physical Verification, Scripting skills, CMOS layout, ASIC design flows, Foundry process requirements"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_9110ed56-39c"},"title":"R&D Engineering, Sr Staff Engineer ICV","description":"<p>Opening. This role exists to manage and provide ICV runset support for key foundry partners, ensuring seamless integration and optimal performance of Synopsys products.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>You will be responsible for delivering post-sales technical expertise throughout the runset programming, implementation, and ongoing maintenance cycles.</p>\n<ul>\n<li>Managing and providing ICV runset support for key foundry partners, ensuring seamless integration and optimal performance of Synopsys products.</li>\n<li>Delivering post-sales technical expertise throughout the runset programming, implementation, and ongoing maintenance cycles.</li>\n<li>Translating detailed customer installation requirements into actionable solutions, customizing product configurations as needed.</li>\n<li>Collaborating with clients to ensure their needs are fully met and Synopsys solutions function according to specifications.</li>\n<li>Offering pre-sales technical support, contributing to sales efforts by addressing technical queries and demonstrating product capabilities.</li>\n<li>Serving as a subject matter expert in EDA tool products, guiding customers through verification, place and route, design reuse, and physical design challenges.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Basic understanding of the design process; familiarity with Design Rule Manuals (DRM) is preferred.</li>\n<li>Strong communication skills, capable of conveying technical concepts clearly to diverse audiences.</li>\n<li>Solid grasp of ASIC design flows, VLSI, and/or CAD engineering principles.</li>\n<li>Experience or knowledge of competitive EDA tool products, with expertise in verification, place and route, design reuse, and/or physical design.</li>\n</ul>\n<p><strong>What you&#39;ll be doing</strong></p>\n<p>You will be working as a Sr Staff Engineer in the R&amp;D Engineering team, responsible for delivering post-sales technical expertise and managing ICV runset support for key foundry partners.</p>\n<p><strong>Why this matters</strong></p>\n<p>This role is critical in ensuring the successful implementation of Synopsys solutions and meeting customer needs.</p>\n<p><strong>Why you&#39;ll love it</strong></p>\n<p>You will have the opportunity to work with a talented team of engineers and contribute to the development of cutting-edge EDA tools.</p>\n<p><strong>What you&#39;ll need</strong></p>\n<ul>\n<li>5+ years of experience in EDA tool development, with a focus on ASIC design flows, VLSI, and/or CAD engineering principles.</li>\n<li>Strong understanding of competitive EDA tool products, with expertise in verification, place and route, design reuse, and/or physical design.</li>\n<li>Excellent communication and problem-solving skills, with the ability to convey technical concepts clearly to diverse audiences.</li>\n<li>Experience working with foundry partners and delivering post-sales technical expertise.</li>\n</ul>\n<p><strong>What you&#39;ll get</strong></p>\n<ul>\n<li>Competitive salary and benefits package.</li>\n<li>Opportunity to work with a talented team of engineers and contribute to the development of cutting-edge EDA tools.</li>\n<li>Professional development opportunities, including training and mentorship.</li>\n</ul>\n<p><strong>How to apply</strong></p>\n<p>If you are a motivated and experienced engineer looking for a new challenge, please submit your application, including your resume and a cover letter, to [insert contact information].</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9110ed56-39c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-staff-engineer-icv/44408/92333269952","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"Competitive salary and benefits package","x-skills-required":["ASIC design flows","VLSI","CAD engineering principles","EDA tool development","Verification","Place and route","Design reuse","Physical design"],"x-skills-preferred":["Foundry partner experience","Post-sales technical expertise","Excellent communication and problem-solving skills"],"datePosted":"2026-03-04T17:06:44.108Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hsinchu"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC design flows, VLSI, CAD engineering principles, EDA tool development, Verification, Place and route, Design reuse, Physical design, Foundry partner experience, Post-sales technical expertise, Excellent communication and problem-solving skills"}]}