{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/design-compiler"},"x-facet":{"type":"skill","slug":"design-compiler","display":"Design Compiler","count":14},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_524edc8e-463"},"title":"ASIC Physical Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Staff Engineer in ASIC Physical Design, you will contribute to the development of cutting-edge semiconductor solutions, working on complex tasks such as chip architecture, circuit design, and verification. You will be responsible for designing and implementing physical design flows, including floor planning, synthesis, placement and routing, timing closure, and physical verification.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.</li>\n<li>Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.</li>\n<li>Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</li>\n<li>Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).</li>\n<li>Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.</li>\n<li>Driving tool flow automation and debugging to enhance productivity and design reliability.</li>\n<li>Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Enable robust validation of Synopsys&#39;s IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.</li>\n<li>Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.</li>\n<li>Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.</li>\n<li>Bolster Synopsys&#39;s reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.</li>\n<li>Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.</li>\n<li>Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>6 to 7 years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep expertise in the complete ASIC physical design flow: floorplanning, synthesis, P&amp;R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.</li>\n<li>Familiarity with IP integration, test chip methodology, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.</li>\n<li>Experience coordinating complex, cross-functional projects and leading technical execution.</li>\n<li>Authorization to work in the USA.</li>\n</ul>\n<p>Team:</p>\n<p>You&#39;ll join the Test Chip PHY development team within Synopsys&#39;s Silicon IP business. This group is dedicated to integrating and validating Synopsys&#39;s broad portfolio of IP blocks -logic, memory, interfaces, analog, security, and embedded processors into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_524edc8e-463","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/asic-physical-design-staff-engineer-16723/44408/93743819104","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","RTL-to-GDSII flow","Static timing analysis","Physical verification","Floor planning","Synthesis","Placement and routing","Timing closure","IP integration","Test chip methodology","Advanced verification flows","CAD tools","Design Compiler","PrimeTime","IC Compiler II/FC","ICV","Calibre","RedHawk","FinFet technologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:19:07.430Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, RTL-to-GDSII flow, Static timing analysis, Physical verification, Floor planning, Synthesis, Placement and routing, Timing closure, IP integration, Test chip methodology, Advanced verification flows, CAD tools, Design Compiler, PrimeTime, IC Compiler II/FC, ICV, Calibre, RedHawk, FinFet technologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cd352346-abd"},"title":"ASIC Physical Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutionsΈ. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly skilled ASIC Physical Design Staff Engineer to join our team. As a Staff Engineer, you will be responsible for implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes, ensuring world-class performance and quality. You will also drive timing closure efforts, especially above ~2GHz, and resolve complex challenges related to mixed signal and macro IP integration.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes</li>\n<li>Driving timing closure efforts, especially above ~2GHz</li>\n<li>Resolving complex challenges related to mixed signal and macro IP integration</li>\n<li>Designing and optimizing clock trees with tight skew balancing to meet stringent performance requirements</li>\n<li>Collaborating daily with local and US counterparts, contributing to technical discussions, and sharing best practices across teams</li>\n<li>Leading project tasks independently, providing regular updates to management, and representing the organization in business unit and company-wide projects</li>\n<li>Mentoring junior engineers, guiding them through technical challenges, and fostering a culture of continuous learning and innovation</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum 6 years of experience in ASIC physical design, preferably with post-graduate qualifications</li>\n<li>Expertise in tools such as Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), and Formality (FC)</li>\n<li>Proven experience with DDR/HBM/HBI timing closure, implementation, and IP integration</li>\n<li>Strong analytical and problem-solving skills, with a track record of resolving complex technical issues</li>\n<li>Ability to independently lead project tasks, mentor junior team members, and work collaboratively</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans</li>\n<li>Time away from work for vacation, sick leave, and family care</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>ESPP (Employee Stock Purchase Plan)</li>\n<li>Retirement plans</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cd352346-abd","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-physical-design-staff-engineer/44408/94169001536","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR/HBM/HBI IP integration","Timing closure","Mixed signal and macro IP integration","Clock tree design"],"x-skills-preferred":["Design Compiler (DC)","IC Compiler II (ICC2)","PrimeTime SI (PT-SI)","Formality (FC)"],"datePosted":"2026-04-24T14:16:07.686Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR/HBM/HBI IP integration, Timing closure, Mixed signal and macro IP integration, Clock tree design, Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), Formality (FC)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cdd41515-ded"},"title":"SOC Engineering, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges.</p>\n<p>Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n</ul>\n<ul>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n</ul>\n<ul>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n</ul>\n<ul>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n</ul>\n<ul>\n<li>Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n</ul>\n<ul>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n</ul>\n<ul>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n</ul>\n<ul>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n</ul>\n<ul>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n</ul>\n<ul>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n</ul>\n<ul>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n</ul>\n<ul>\n<li>Support strategic customer engagements and help expand Synopsys&#39; presence in the semiconductor ecosystem through successful project outcomes.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cdd41515-ded","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-engineering-staff-engineer/44408/94169001488","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimization","static timing analysis (STA)","physical verification","EMIR analysis","timing closure","block-level and full-chip floor-planning","Python","PERL","TCL","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:15:21.802Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimization, static timing analysis (STA), physical verification, EMIR analysis, timing closure, block-level and full-chip floor-planning, Python, PERL, TCL, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_642c88a4-a92"},"title":"ASIC Physical Design, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Sr Staff Engineer in ASIC Physical Design, you will contribute to the development of advanced semiconductor solutions, collaborating with cross-functional teams to design, verify, and manufacture complex SoCs and test chips. Your expertise in the physical design flow and familiarity with industry-leading tools will enable you to drive technical execution and lead complex projects.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.</li>\n<li>Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.</li>\n<li>Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</li>\n<li>Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).</li>\n<li>Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.</li>\n<li>Driving tool flow automation and debugging to enhance productivity and design reliability.</li>\n<li>Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Enable robust validation of Synopsys&#39;s IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.</li>\n<li>Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.</li>\n<li>Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.</li>\n<li>Bolster Synopsys&#39;s reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.</li>\n<li>Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.</li>\n<li>Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>9+ years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep expertise in the complete ASIC physical design flow: floor planning, synthesis, P&amp;R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.</li>\n<li>Familiarity with IP integration, test chip methodology, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.</li>\n<li>Experience coordinating complex, cross-functional projects and leading technical execution.</li>\n<li>Authorization to work in the USA.</li>\n</ul>\n<p>Team:</p>\n<p>You&#39;ll join the Test Chip PHY development team within Synopsys&#39;s Silicon IP business. This group is dedicated to integrating and validating Synopsys&#39;s broad portfolio of IP blocks,logic, memory, interfaces, analog, security, and embedded processors,into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_642c88a4-a92","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/asic-physical-design-sr-staff-engineer-16724/44408/93743819072","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","RTL-to-GDSII flow","Static timing analysis","Physical verification","Design Compiler","PrimeTime","IC Compiler II/FC","Calibre","RedHawk","FinFet technologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:12:52.721Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, RTL-to-GDSII flow, Static timing analysis, Physical verification, Design Compiler, PrimeTime, IC Compiler II/FC, Calibre, RedHawk, FinFet technologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7375c418-b8a"},"title":"SOC Engineering, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Sr Staff Engineer in SOC Engineering, you will independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs. You will execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm)</li>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets</li>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities</li>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence</li>\n<li>Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions</li>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency</li>\n</ul>\n<p>Key Requirements:</p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field</li>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm)</li>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimization, STA, EMIR, and physical verification</li>\n<li>Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime</li>\n<li>Strong scripting and automation skills using Python, PERL, TCL, or similar languages</li>\n<li>Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs</li>\n<li>Exposure to high-frequency design and low-power design methodologies</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back</li>\n</ul>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7375c418-b8a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/soc-engineering-sr-staff-engineer/44408/94212497968","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$120,000 - $180,000 per year","x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimization","static timing analysis (STA)","physical verification","EMIR analysis","timing closure","floor-planning","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime","Python","PERL","TCL","high-frequency design","low-power design methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:12:44.698Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimization, static timing analysis (STA), physical verification, EMIR analysis, timing closure, floor-planning, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, Python, PERL, TCL, high-frequency design, low-power design methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":120000,"maxValue":180000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4f7dae70-9ee"},"title":"R&D Engineer, Staff (PD, PnR, CTS)","description":"<p>Join Synopsys as a Staff R&amp;D Engineer in Physical Design (PD), Place and Route (PnR), and Chip Technology Software (CTS). As a member of our Hardware-Analytics and Test (HAT) business unit, you will be part of the SLM Hardware Group (SHG) developing advanced SLM IPs and subsystems.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Design and implement physical design flows for SLM IPs and subsystems, including state-of-the-art SLM Controllers and on-chip Monitors.</li>\n<li>Execute RTL2GDS flows on advanced process nodes (16nm to 3nm and beyond), ensuring robust performance and reliability.</li>\n<li>Perform static timing analysis, synthesis, and layout closure using industry-leading EDA tools, preferably Synopsys PrimeTime, ICC2, Design Compiler, or Fusion Compiler.</li>\n<li>Collaborate with cross-functional teams to integrate soft and mixed-signal IPs, optimize design margins, and address high-frequency, multi-voltage, and low-power requirements.</li>\n<li>Develop and enhance automation scripts (TCL/PERL) to streamline design processes and improve execution efficiency.</li>\n<li>Participate in project planning, execution, and mentoring, supporting both internal teams and external customers with technical expertise and guidance.</li>\n<li>Contribute to the signoff and verification of designs, ensuring compliance with quality and reliability standards.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Accelerate the integration and deployment of next-generation SLM products, enabling customers to bring differentiated solutions to market faster and with reduced risk.</li>\n<li>Optimize semiconductor lifecycle management through innovative hardware IP, test, and analytics, enhancing performance, power, area, and yield.</li>\n<li>Drive advancements in chip design and verification methodologies, supporting the evolution of process nodes and IP integration.</li>\n<li>Enhance reliability and scalability of technology products, contributing to breakthroughs in AI, IoT, automotive, and cloud sectors.</li>\n<li>Empower global teams and customers with robust solutions, technical guidance, and effective collaboration.</li>\n<li>Support Synopsys&#39; leadership in the Era of Smart Everything, powering the technologies that shape our connected world.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Strong experience in standard ASIC RTL2GDS physical implementation and signoff flows.</li>\n<li>Hands-on expertise in synthesis, pre-layout STA, post-layout STA, and CTS tools.</li>\n<li>BS or MS degree in Electrical Engineering with 5+ years of relevant industry experience.</li>\n<li>Automation-focused mindset with proven experience in scripting (TCL/PERL) and custom flow development.</li>\n<li>Exposure to soft and mixed-signal IPs, high-frequency/multi-voltage designs, and low-power methodologies.</li>\n<li>Proficiency with EDA tools from any vendor, preferably Synopsys tools (PrimeTime, ICC2, Design Compiler, Fusion Compiler).</li>\n<li>Solid understanding of OCV, POCV, derates, crosstalk, and design margins.</li>\n<li>Experience in layout of digital blocks, timing constraints, STA, and timing closure.</li>\n<li>Experience with PVT-sensors and/or DFT/DFx technologies is a strong plus.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Collaborative and inclusive team player who values diversity and supports others.</li>\n<li>Excellent communicator, able to convey complex technical concepts clearly and effectively.</li>\n<li>Mentor and leader, providing guidance and support to peers and junior engineers.</li>\n<li>Adaptable and innovative, eager to learn and embrace new technologies and methodologies.</li>\n<li>Self-motivated with strong project execution and planning skills.</li>\n<li>Customer-focused, dedicated to delivering high-quality solutions and support.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join the rapidly expanding Hardware-Analytics and Test (HAT) business unit as a member of the SLM Hardware Group (SHG). The team is dedicated to developing advanced SLM IPs and subsystems, leveraging expertise in backend and physical design to deliver robust, high-performance solutions.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4f7dae70-9ee","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/r-and-d-engineer-staff-pd-pnr-cts/44408/93647959680","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDS physical implementation","Synthesis","Static timing analysis","Place and route","Layout closure","Automation scripting","TCL/PERL","EDA tools","Synopsys PrimeTime","ICC2","Design Compiler","Fusion Compiler","Soft and mixed-signal IPs","High-frequency/multi-voltage designs","Low-power methodologies","PVT-sensors","DFT/DFx technologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:12:09.026Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDS physical implementation, Synthesis, Static timing analysis, Place and route, Layout closure, Automation scripting, TCL/PERL, EDA tools, Synopsys PrimeTime, ICC2, Design Compiler, Fusion Compiler, Soft and mixed-signal IPs, High-frequency/multi-voltage designs, Low-power methodologies, PVT-sensors, DFT/DFx technologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a8553e18-093"},"title":"DFT Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a DFT Staff Engineer, you will own DFT tasks such as scan chain stitching, ATPG, and simulation. You will create timing constraints for mission and DFT modes, work with design and implementation teams, and support customer IP integration and silicon bring-up. You will also automate workflows with scripting and mentor junior team members.</p>\n<p>The impact you will have is enhancing IP core testability and quality, accelerating time-to-market for new chipsets, facilitating seamless SoC integration, promoting best practices and team growth, advancing DFT methodologies at Synopsys, and supporting customers during silicon bring-up.</p>\n<p>To succeed in this role, you will need a degree in Electronics, Electrical Engineering, or a related field. No DFT experience is required for junior roles, but 6+ years of experience is needed for senior roles. You should have knowledge of scan insertion, ATPG, JTAG, and experience with Synopsys tools such as Design Compiler, VCS, and TetraMAX. Scripting skills in Perl, TCL, or Python are also desirable.</p>\n<p>You will be analytical, detail-oriented, proactive, collaborative, and communicative. You will be adaptable and eager to learn, with a passion for chip testability and reliability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a8553e18-093","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/dft-staff-engineer/44408/94018015184","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["scan insertion","ATPG","JTAG","Design Compiler","VCS","TetraMAX","Perl","TCL","Python"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:11:15.225Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"scan insertion, ATPG, JTAG, Design Compiler, VCS, TetraMAX, Perl, TCL, Python"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c12edbfc-7a0"},"title":"DFT Junior Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>The role involves intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a DFT Junior Engineer, you will own DFT tasks, create timing constraints for mission and DFT modes, work with design and implementation teams, support customer IP integration and silicon bring-up, automate workflows with scripting, and mentor junior team members.</p>\n<p>The impact you will have includes enhancing IP core testability and quality, accelerating time-to-market for new chipsets, facilitating seamless SoC integration, promoting best practices and team growth, advancing DFT methodologies at Synopsys, and supporting customers during silicon bring-up.</p>\n<p>To be successful in this role, you will need a degree in Electronics, Electrical Engineering, or a related field, no DFT experience required for junior roles, knowledge of scan insertion, ATPG, JTAG, experience with Synopsys tools (Design Compiler, VCS, TetraMAX) preferred, and scripting skills (Perl, TCL, Python).</p>\n<p>You will be an analytical, detail-oriented, proactive, collaborative and communicative individual who is adaptable and eager to learn.</p>\n<p>Join a skilled DFT engineering team that values collaboration, innovation, and technical excellence. Benefit from mentorship and tackle industry-leading challenges together.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more about salary and benefits during the process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c12edbfc-7a0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/dft-junior-engineer-in-hcmc-ha-noi-da-nang/44408/92864858752","x-work-arrangement":"onsite","x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["scan insertion","ATPG","JTAG","Synopsys tools (Design Compiler, VCS, TetraMAX)","scripting skills (Perl, TCL, Python)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:23:13.711Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"scan insertion, ATPG, JTAG, Synopsys tools (Design Compiler, VCS, TetraMAX), scripting skills (Perl, TCL, Python)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c01e313a-c5a"},"title":"IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer","description":"<p>We&#39;re looking for an IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer to join our team.</p>\n<p>Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.</li>\n<li>Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.</li>\n<li>Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum 5+ years of experience in IP/ASIC/SOC design implementation.</li>\n<li>Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.</li>\n<li>Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.</li>\n<li>Good communication skills while interacting with internal teams and customers.</li>\n</ul>\n<p>Preferred Experience:</p>\n<ul>\n<li>Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.</li>\n<li>Experience in DesignWare Core IPs or PHYs.</li>\n<li>Experience in TCL, Perl, Python, or other shell scripting.</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Competitive salary and benefits package.</li>\n<li>Opportunities for professional growth and development.</li>\n<li>Collaborative and dynamic work environment.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c01e313a-c5a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/shanghai/ip-pcie-cxl-usb-dp-subsystem-design-implementation-engineer/44408/92638132304","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["IP/ASIC/SOC design implementation","synthesis","timing optimization","SDC writing","CDC/RDC checking","PCIe","USB","Display Port","Ethernet","DDR"],"x-skills-preferred":["Design Compiler","Fusion Compiler","PrimeTime","Spyglass","VC Spyglass","DesignWare Core IPs","PHYs","TCL","Perl","Python","shell scripting"],"datePosted":"2026-04-05T13:22:43.150Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Shanghai"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"IP/ASIC/SOC design implementation, synthesis, timing optimization, SDC writing, CDC/RDC checking, PCIe, USB, Display Port, Ethernet, DDR, Design Compiler, Fusion Compiler, PrimeTime, Spyglass, VC Spyglass, DesignWare Core IPs, PHYs, TCL, Perl, Python, shell scripting"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7c858523-91f"},"title":"SOC Engineering, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.</p>\n<p>Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n<li>Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n<li>Support strategic customer engagements and help expand Synopsys&#39; presence in the semiconductor ecosystem through successful project outcomes.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.</li>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).</li>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimisation, STA, EMIR, and physical verification.</li>\n<li>Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.</li>\n<li>Strong scripting and automation skills using Python, PERL, TCL, or similar languages.</li>\n<li>Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.</li>\n<li>Exposure to high-frequency design and low-power design methodologies.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Proactive, self-motivated, and driven to achieve technical excellence.</li>\n<li>Exceptional problem-solving and analytical skills with a keen attention to detail.</li>\n<li>Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.</li>\n<li>Collaborative team player who values knowledge sharing and mentoring others.</li>\n<li>Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</p>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>** Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7c858523-91f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-engineering-staff-engineer/44408/92684730800","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimisation","static timing analysis (STA)","physical verification","block-level and full-chip floor-planning","EMIR analysis","timing closure","Python","PERL","TCL","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime"],"x-skills-preferred":["high-frequency design","low-power design methodologies","collaboration","problem-solving","analytical skills","communication","interpersonal abilities"],"datePosted":"2026-04-05T13:22:21.047Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimisation, static timing analysis (STA), physical verification, block-level and full-chip floor-planning, EMIR analysis, timing closure, Python, PERL, TCL, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, high-frequency design, low-power design methodologies, collaboration, problem-solving, analytical skills, communication, interpersonal abilities"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b4e4a0dc-158"},"title":"DFT, Staff Engineer","description":"<p><strong>Overview</strong></p>\n<p>At Synopsys, our Hardware Engineers are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15995</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>03/05/2026</p>\n<p><strong>Alternate Job Titles:</strong></p>\n<ul>\n<li>Staff ASIC Digital Design Engineer</li>\n</ul>\n<ul>\n<li>Staff DFT Engineer</li>\n</ul>\n<ul>\n<li>Staff SoC Testability Engineer</li>\n</ul>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive innovations that shape the way we live and connect. From smart cars to AI, our technology leads chip design and verification worldwide. Join us to transform the future through continuous innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a proactive engineer with 5+ years of DFT experience, strong communication skills, and a drive for technical excellence. You enjoy teamwork, learning, and solving complex challenges in digital design.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Define and implement DFT architecture for IP designs</li>\n</ul>\n<ul>\n<li>Perform SCAN insertion and ATPG simulation</li>\n</ul>\n<ul>\n<li>Analyze and improve test coverage</li>\n</ul>\n<ul>\n<li>Develop STA DFT timing constraints</li>\n</ul>\n<ul>\n<li>Prepare DFT integration guidelines for SoC</li>\n</ul>\n<ul>\n<li>Conduct quality checks and FMEDA/DFMEA analysis</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enhance product reliability and quality</li>\n</ul>\n<ul>\n<li>Support functional safety standards (ISO26262, FUSA)</li>\n</ul>\n<ul>\n<li>Streamline SoC integration</li>\n</ul>\n<ul>\n<li>Reduce debug cycles and time-to-market</li>\n</ul>\n<ul>\n<li>Mentor peers</li>\n</ul>\n<ul>\n<li>Drive innovation in test methodology</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>BS/MS/PhD in Electronics or related field</li>\n</ul>\n<ul>\n<li>5+ years DFT design experience</li>\n</ul>\n<ul>\n<li>Expertise in Scan insertion, ATPG, JTAG</li>\n</ul>\n<ul>\n<li>Experience with Synopsys tools (Design Compiler, VCS, TetraMAX)</li>\n</ul>\n<ul>\n<li>Scripting (Perl, TCL, Python) is a plus</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Responsible and collaborative</li>\n</ul>\n<ul>\n<li>Excellent English communication</li>\n</ul>\n<ul>\n<li>Team player and problem solver</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>Join a skilled, diverse engineering team in Da Nang focused on advancing DFT methodologies and supporting global innovation.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will provide more details during the hiring process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b4e4a0dc-158","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hanoi/dft-staff-engineer-in-hcmc-hanoi/44408/92454718736","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["DFT design experience","Scan insertion","ATPG","JTAG","Synopsys tools (Design Compiler, VCS, TetraMAX)","Scripting (Perl, TCL, Python)"],"x-skills-preferred":[],"datePosted":"2026-03-08T22:19:13.522Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hanoi"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"DFT design experience, Scan insertion, ATPG, JTAG, Synopsys tools (Design Compiler, VCS, TetraMAX), Scripting (Perl, TCL, Python)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_04934540-478"},"title":"Physical Design Specialist (PDS)","description":"<p>We are looking for a Physical Design Specialist (PDS) to join our team. In this role, you will be responsible for supporting the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>The primary focus of the Physical Design Specialist (PDS) is to support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</li>\n<li>In addition, PDS AEs will articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)</li>\n<li>RTL to GDSII full flow experience or knowledge is preferable</li>\n<li>Strong interest and understanding of Advanced Node &amp; Design methodologies are required.</li>\n<li>In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.</li>\n<li>Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred</li>\n<li>Excellent verbal and written presentation/communication skills are mandatory.</li>\n<li>Customer sensitivity, the ability to multiplex many issues &amp; set priorities, and the desire to help customers exploit new technologies are essential for success in the position.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_04934540-478","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/applications-engineering-principal-engineer/44408/90265976416","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Design Implementation experience","RTL to GDSII full flow experience","Strong interest and understanding of Advanced Node & Design methodologies","In-depth Synopsys Back end tool experience","Knowledge of several Clock Tree Synthesis methodologies","Excellent verbal and written presentation/communication skills","Customer sensitivity"],"x-skills-preferred":["BSEE or equivalent","Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus)","Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus)","Tool knowledge (preferred): STA (Primetime, Tempus)"],"datePosted":"2026-03-06T07:29:04.274Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Design Implementation experience, RTL to GDSII full flow experience, Strong interest and understanding of Advanced Node & Design methodologies, In-depth Synopsys Back end tool experience, Knowledge of several Clock Tree Synthesis methodologies, Excellent verbal and written presentation/communication skills, Customer sensitivity, BSEE or equivalent, Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus), Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus), Tool knowledge (preferred): STA (Primetime, Tempus)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b455ed20-1e0"},"title":"Applications Engineering, Sr Staff Engineer - RTL2GDS Application Specialist","description":"<p>We are seeking a highly skilled Applications Engineering, Sr Staff Engineer - RTL2GDS Application Specialist to join our team. As a key member of our Silicon Design &amp; Verification team, you will be responsible for providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.</li>\n<li>Diagnosing, troubleshooting, and resolving complex technical issues during customer installations and deployments.</li>\n<li>Training customers on new implementations, features, and capabilities of Synopsys RTL2GDS full flow solutions.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Extensive experience with RTL to GDSII full flow and advanced node design methodologies.</li>\n<li>Hands-on proficiency with synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b455ed20-1e0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/applications-engineering-sr-staff-engineer-rtl2gds-application-specialist/44408/92176305600","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$157000-$235000","x-skills-required":["RTL to GDSII full flow","advanced node design methodologies","synthesis","physical design","static timing analysis","equivalence checking","parasitic extraction","DRC/LVS","power analysis"],"x-skills-preferred":["Perl","Tcl","Python","CAD automation methods","Design Compiler","ICC2","Fusion Compiler","Genus","Innovus","STA","IR drop analysis","Extraction","Formal verification"],"datePosted":"2026-03-06T07:26:03.775Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale, California"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL to GDSII full flow, advanced node design methodologies, synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, power analysis, Perl, Tcl, Python, CAD automation methods, Design Compiler, ICC2, Fusion Compiler, Genus, Innovus, STA, IR drop analysis, Extraction, Formal verification","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":157000,"maxValue":235000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7f429a32-e1d"},"title":"Senior Applications Engineer – Interface IP","description":"<p>We are seeking a highly motivated, customer-focused engineering professional to join our team as a Senior Applications Engineer – Interface IP. In this role, you will provide technical guidance and hands-on support to customers integrating Synopsys Interface IP into their ASIC SoC/systems.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems</li>\n<li>Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Masters with 10+yrs of Industry experience or equivalent</li>\n<li>At least 10+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered)</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7f429a32-e1d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/applications-engineering-principal-engineer/44408/92341044400","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["IP design","ASIC/SoC integration","customer-facing engineering"],"x-skills-preferred":["RTL and gate-level simulation debugging","front-end tools like Design Compiler, Fusion Compiler, and PrimeTime"],"datePosted":"2026-03-06T07:23:41.768Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"IP design, ASIC/SoC integration, customer-facing engineering, RTL and gate-level simulation debugging, front-end tools like Design Compiler, Fusion Compiler, and PrimeTime"}]}