These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a visionary leader and seasoned layout design professional, passionate about advancing the frontiers of semiconductor technology. With over eight years of hands-on experience, you thrive in dynamic environments where innovation and technical excellence are paramount.

You possess a deep understanding of deep submicron effects, advanced floorplanning techniques, and process technologies like CMOS, FinFET, and GAA at 7nm and below. Your expertise extends to layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, and IO frame and pitch requirements.

You are adept at leading multi-disciplinary teams, creating an environment of accountability, ownership, and growth, while mentoring junior engineers and empowering senior team members to excel.

You value diversity and inclusion, fostering a culture where every voice is heard and respected. Your collaborative approach ensures seamless cross-functional coordination, and you have a knack for translating complex technical requirements into actionable project plans.

Your communication skills,both written and verbal,enable you to engage effectively with stakeholders at all levels. You are motivated by the opportunity to contribute to high-impact projects, drive innovation in DDR/HBM PHY IP layout, and deliver differentiated products that shape the industry.

If you are ready to lead, inspire, and make a lasting impact, Synopsys is the place for you.

Leading the development of next-generation DDR/HBM IP layouts, driving technical innovation and quality excellence.

Mentoring and managing a team of layout engineers, fostering growth and maximizing individual and team potential.

Developing and maintaining project schedules, ensuring timely delivery while balancing technical and resource constraints.

Collaborating cross-functionally with design, verification, and IP teams to align on project requirements and execution.

Providing subject matter expertise in high-speed DDR/HBM IP layout, including floorplanning, layout reviews, and quality checks.

Executing layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO requirement analysis.

Supporting layout automation through scripting and tool enhancement, optimizing efficiency and productivity.

Acting as an advisor to resolve project challenges and guide teams towards innovative solutions.

Accelerating the integration of advanced capabilities into SoCs, helping customers achieve unique performance, power, and size targets.

Reducing time-to-market and risk for differentiated products through robust layout design and technical leadership.

Driving continuous improvement in layout methodologies and quality standards across cross-functional teams.

Empowering your team to deliver high-performance DDR/HBM PHY IPs that set industry benchmarks.

Fostering a collaborative, inclusive work environment that values innovation, accountability, and diversity.

Contributing to Synopsys’ reputation as the provider of the world’s broadest portfolio of silicon IP.

Shaping the future of chip design and verification technologies through your expertise and leadership.

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