At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nYou are a dynamic engineer with working experience in RTL implementation, DFT, verification, flow automation and understanding of 3DIC solutions and UCIe protocols. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them at our premier customer base. Your technical excellence and analytical skills, coupled with strong communication and interpersonal skills, make you an asset to any team.
\nKey responsibilities include:
\nWorking closely with a world-class R&D team, you’ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) and 3DIC technologies.
\nWorking closely with customers, you will bring detailed requirements into the factory to enable R&D for strong, robust, and successful product development.
\nWorking closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.
\nDriving the deployment and smooth execution of SLM solutions into customers’ projects.
\nEnabling customers to realize the value of silicon health monitoring in the context of 3DIC systems throughout the lifecycle of silicon bring-up, validation, through in-field operations.
\nThe impact you will have includes enhancing Synopsys’ Silicon Lifecycle Management (SLM) and 3DIC solutions’ IP portfolio and end-to-end solution especially in the growing field of multi-die (3DIC) domain, driving the adoption of Synopsys’ SLM and 3DIC solutions at premier customer base worldwide, and influencing the development of next-generation SLM IPs and solutions.
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\nAs a Staff ASIC Digital Design Engineer, you will be part of our R&D Professional team, specializing in mixed-signal ASIC development and supporting HBM/DDR PHY IP customers. You will work with experts in design, implementation, and verification.
\nKey responsibilities include:
\nCreating and debugging test benches and test cases\nRunning RTL and gate-level simulations\nSupporting application engineers and customers on HBM/DDR PHY topics\nContributing to technical documentation\nDriving product improvements based on customer feedback
\nThe ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:
\nASIC RTL design and verification experience\nVerilog, PERL, TCL, Python skills\nStatic timing analysis and synthesis knowledge\nSimulation and debugging abilities\nHBM/DDR protocol experience is an asset
\nWe offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and perks during the hiring process.
\nXML job scraping automation by YubHub
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