Your responsibilities will include driving down costs through automation, less TOIL and efficient use of Infrastructure, evaluating the SWIFT product and services from functional and non-functional perspective, and delivering change program as per the annual Book of Work. You will also be responsible for collecting resource and cost estimates, establishing baseline budgets, and securing approvals from the Program Steering Committee, tracking expenses against approved budgets and providing monthly progress reports to stakeholders, conducting revenue projections to support business cases, identifying cost savings, and optimizing resource allocation.

Additionally, you will be responsible for the budget management and reporting for SWIFT Alliance Gateway USA, identifying and managing risks, dependencies, and compliance requirements throughout the service lifecycle, ensuring all functional and regulatory standards are met. You will perform periodic risk assessments, enforce HSBC's Enterprise and Operational Risk Management Frameworks, and maintain robust control documentation.

You will participate in audits and implement all security and data privacy controls as per compliance standards, leading program governance forums, project kickoff meetings, and project status updates, and facilitating cross-team collaboration. You will define and execute a detailed communication plan, including escalation protocols and risk communication, maintaining strong working relationships with cross-functional teams, vendors, and resource managers, ensuring alignment with project goals.

This is a full-time position, Monday-Friday, 40 hours per week, with telecommuting permitted up to 100% from anywhere in the US.

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For example, you might:

• Research the science of AI agent capabilities with a focus on how they relate to safety, risk factors, and methodologies for benchmarking them;
• Design and build harnesses to test AI agents' tendency to take harmful actions when pressured to do so by users or tricked into doing so by elements of their environment;
• Design and build exploits and mitigations for new and unique failure modes that arise as AI agents gain affordances like coding, web browsing, and computer use;
• Characterize and design mitigations for potential failure modes or broader risks of systems involving multiple interacting AI agents.

Ideally you'd have:

• Commitment to our mission of promoting safe, secure, and trustworthy AI deployments in the industry as frontier AI capabilities continue to advance;
• Practical experience conducting technical research collaboratively;
• Experience with post-training and RL techniques such as RLHF, DPO, GRPO, and similar approaches;
• A track record of published research in machine learning, particularly in generative AI;
• At least three years of experience addressing sophisticated ML problems, whether in a research setting or in product development;
• Strong written and verbal communication skills to operate in a cross-functional team.

Nice to have:

• Hands-on experience with agent evaluation frameworks such as SWE-bench, WebArena, OSWorld, Inspect, or similar tools;
• Experience with red-teaming, prompt injection, or adversarial testing of AI systems.

Our research interviews are crafted to assess candidates' skills in practical ML prototyping and debugging, their grasp of research concepts, and their alignment with our organisational culture. We will not ask any LeetCode-style questions. If you're excited about advancing AI safety and contributing to our mission, we encourage you to apply, even if your experience doesn't perfectly align with every requirement.

Compensation packages at Scale for eligible roles include base salary, equity, and benefits. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position, determined by work location and additional factors, including job-related skills, experience, interview performance, and relevant education or training. Scale employees in eligible roles are also granted equity-based compensation, subject to Board of Director approval. Your recruiter can share more about the specific salary range for your preferred location during the hiring process, and confirm whether the hired role will be eligible for equity grant. You'll also receive benefits including, but not limited to: Comprehensive health, dental and vision coverage, retirement benefits, a learning and development stipend, and generous PTO. Additionally, this role may be eligible for additional benefits such as a commuter stipend.

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We protect and accelerate any Internet application online without adding hardware, installing software, or changing a line of code. Internet properties powered by Cloudflare all have web traffic routed through its intelligent global network, which gets smarter with every request. As a result, they see significant improvement in performance and a decrease in spam and other attacks.

Available Locations: Austin, TX

About the role

Cloudflare One is our SASE platform that is redefining how the world's most sophisticated organisations secure and connect their global workforce. By unifying Zero Trust Network Access (ZTNA), Secure Web Gateway (SWG), Wide Area Network (WAN) and Cloud Access Security Broker (CASB) as well as Email Security into a single, seamless SASE architecture, we are moving the industry beyond the legacy 'castle-and-moat' era.

What you'll do

We are looking for a product leader to lead the Cloudflare One portfolio. You are not someone to simply manage a steady ship; you are someone to invent the next generation of Access, Gateway, and WAN, unlocking new Total Addressable Markets (TAM) in the SASE space while executing your way into being the market leader for the current Service Addressable Market (SAM).

Desirable Skills, Knowledge, and Experience:

• A deep empathy for customers and an understanding of the fundamental shifts happening in technology, the SSE and SASE space, especially around AI

• Proven experience in a senior leadership role (e.g., former founder, Sr. Director, VP, CTO), having built and scaled both products and teams

• An entrepreneurial spirit with enterprise etiquette and a history of building things, whether in a successful venture or a passionate side project

• Proven ability to pivot instantly from technical deep-dives to high-level strategic discussions

Must-Have Skills

• 12+ years of experience in product management or a closely related role, with a focus on network and data security technologies (e.g., ZTNA, Gateways, DLP, CASB, data encryption, data classification, data privacy)

• Own the SASE product roadmap. Make tough tactical prioritization decisions while helping the company think long-term. Build trust with stakeholders by maintaining an understandable, accurate roadmap

• Partner with leaders in other departments such as Product Marketing, Marketing, Sales, and Customer Support to drive adoption with and gather feedback from customers and prospects

• Develop and nurture relationships with engineering leadership and coordinate closely to ensure successful delivery of product

• Deep understanding of the network and security landscapes, including current trends and threats, regulatory requirements, and emerging technologies

Nice to haves

• An understanding and real-world experience working with all types of channel partners (VARs, MSP, MSSP, etc)

• A Computer Science degree or equivalent in-seat experience in product roles for technical products is highly preferred

• Experience leading product integrations during post-merger acquisitions (M&A)

• Deep familiarity with Zero Trust architecture and SD-WAN markets

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At Coinbase, our mission is to increase economic freedom in the world.

We're seeking an experienced Engineering Manager to lead the Ledger team within the Product Foundations - Platform Product Group.

Ledger is one of the core services for Coinbase, responsible for processing transactions and managing the funds of our users.

As one of Coinbase's most mission-critical services, Ledger sits at the core of our platform, processing billions in transactions and securing the assets of millions of users.

Today, our scale and complexity of operations have far surpassed the original design of Ledger and fund management systems.

This presents a rare and exciting opportunity to rearchitect foundational infrastructure that will shape Coinbase's success for the next decade.

Responsibilities:

• Build and manage engineering teams, to guide the development of features, services, and infrastructure.

• Coach your direct reports to have a positive impact on the organization and support their career growth.

• Implement the multi-year strategy for our team and collaborate with engineers, designers, product managers and senior leadership to turn our vision into a tangible roadmap every quarter.

• Be a thoughtful technical voice within the team, aiding in diligent architectural decisions and fostering a culture of high-quality code and engineering processes.

• Collaborate with Product and Engineering teams to ensure successful delivery and operation of multi-tenanted, distributed systems at scale.

• Work closely with our talent organization to identify and recruit exceptional engineers who align with Coinbase's culture and will help the team scale.

• Contribute to and take ownership of processes that drive engineering quality and meet our engineering SLAs.

What We Look For In You:

• At least 7 years of experience in software engineering.

• At least 2 years of engineering management experience.

• You possess a strong understanding of what constitutes high-quality code and effective engineering practices.

• An execution-focused mindset, capable of navigating through ambiguity and delivering results.

• An ability to balance long-term strategic thinking with short-term planning.

• Experience in creating, delivering, and operating multi-tenanted, distributed systems at scale.

• You can be hands-on when needed – whether that’s writing/reviewing code or technical documents, participating in on-call rotations and leading incidents, or triaging/troubleshooting bugs.

• Demonstrates the ability to responsibly use generative AI tools and copilots (e.g., LibreChat, Gemini, Glean) in daily workflows, continuously learn as tools evolve, and apply human‑in‑the‑loop practices to deliver business‑ready outputs and drive measurable improvements in efficiency, cost, and quality.

Nice to haves:

• Prior experience leading a Platform or similar domain team.

• Experience designing and operating ledgering or trading systems at scale.

• Experience with financial data, accounting systems, or high-precision transaction processing.

• Experience with Go, Kubernetes, Postgres, or similar technologies.

• You have gone through a rapid growth in your company (from startup to mid-size).

• Crypto-forward experience, including familiarity with onchain activity such as interacting with Ethereum addresses, using ENS, and engaging with dApps or blockchain-based services.

Job #: P76571

Pay Transparency Notice: Depending on your work location, the target annual base salary for this position can range as detailed below.

Total compensation may also include equity and bonus eligibility and benefits (including medical, dental, vision and 401(k)).

Annual base salary range (excluding equity and bonus):

$218,025-$256,500 USD

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As a Senior Circuit Designer, you will be responsible for designing embedded electronics from concept to functional prototype, including hardware selection, schematic & PCB design, board bring-up, and system level integration.

You will work closely with firmware/software engineers for processor/peripheral selection, board bring up, and troubleshooting.

You will also work in a fast-paced environment supporting new developments, active deployments, and customer operated hardware.

Concurrently, you will manage involvement in multiple projects at various stages.

Required qualifications include a Bachelor’s Degree in Electrical Engineering and 10+ years of experience designing, testing, and troubleshooting complex hardware, embedded systems, and products.

Experience with multi-gigabit SERDES, DDR memory busses, Ethernet MAC and PHY interfaces, FPGAs, and common communication busses like SPI and I2C is also required.

Additionally, you should have experience with microprocessor and microcontroller selection, configuration, and interfacing, as well as competence with test equipment such as oscilloscopes, logic analyzers, debuggers, current-probes, and automation of tests.

Exceptional organization and communication skills are also necessary.

Salary range: $146,000-$194,000 USD.

Benefits include comprehensive medical, dental, and vision plans, income protection, generous time off, family planning & parenting support, mental health resources, professional development, commuter benefits, relocation assistance, and a retirement savings plan.

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In this role, you will work closely with an interdisciplinary technical team to route high-speed mixed-signal designs, interact with fabricators and assemblers, and manage signal integrity in complex PCBs.

Key responsibilities include:

• Working directly with engineers to produce printed circuit board designs supporting Anduril's products.
• Applying modern design standards and guidelines to create high-reliability, highly manufacturable assemblies.
• Implementing combinations of high-speed digital, precision analog, RF, and high-power designs.
• Leading the team in establishing internal guidelines for design for manufacturing (DFM), design for assembly (DFA), and overall quality fabrication and assembly outputs.
• Developing and refining team processes for PCB design, part creation, and library/database standards.
• Coordinating external PCB design resources during design surges.

Required qualifications include:

• A bachelor's degree in electrical engineering or similar and 5+ years of professional experience in PCB design OR 10+ years of professional experience in PCB design.
• Ability to read and interpret schematics and apply best practices appropriate for each design.
• Expertise in applying relevant IPC standards, CID, CID+ certification.
• Expertise in PCB fabrication processes, limitations, design rules, and best practice.
• Experience using Altium Designer CAD tools (Allegro is a plus).
• Experience with developing component libraries and library management.
• Excellent communication skills with multiple fab houses (ensuring boards are built to print).
• Excellent communication skills with multiple assembly houses (ensuring boards are built to BOM).
• Experience with a variety of board types, including high density and high layer count (greater than 16) digital designs, power electronics, flex circuits, and RF circuits.
• Experience with HDI (high density interconnect) and thicker boards (greater than 1.6mm).
• Experience with high speed digital interfaces and controlled impedance routing requirements like USB, PCIe, Ethernet, SERDES, and DDR memory.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Preferred qualifications include:

• Familiarity with RF board design.
• Experience with high-pin count packages (FPGA fanout).
• Familiarity with basic signal and power integrity rules (how they affect layout).

US Salary Range $111,000-$147,000 USD

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In this role, you will own end-to-end Finance & accounting system architecture spanning key business processes around GL, AP, AR, ARM, Fixed Assets, Leases and inventory accounting. You will act as the primary systems partner for Finance stakeholders, including Revenue Accounting, Operations Accounting, Tax, Fixed Assets, Treasury, GL and AP teams, while working with IT Product Management on executing the roadmap across modules aligned with business priorities.

You will lead a team of BSEs and administrators to deliver scalable solutions aligned to business goals, implement and execute audit ready ITGC & ITAC controls for SOX Compliance, and partner with IT integration teams on cross-functional workflows and AI agents for process automation and optimization. You will also provide leadership for Finance systems admin support, GL, and operational excellence.

The base salary range for this role is $207,000 to $250,000. The starting salary will be determined based on job-related knowledge, skills, experience, and market location. We strive for both market alignment and internal equity when determining compensation. In addition to base salary, our total rewards package includes a discretionary bonus, equity awards, and a comprehensive benefits program (all based on eligibility).

The range we’ve posted represents the typical compensation range for this role. To determine actual compensation, we review the market rate for each candidate which can include a variety of factors. These include qualifications, experience, interview performance, and location.

In addition to a competitive salary, we offer a variety of benefits to support your needs, including:

• Medical, dental, and vision insurance - 100% paid for by CoreWeave

• Company-paid Life Insurance

• Voluntary supplemental life insurance

• Short and long-term disability insurance

• Flexible Spending Account

• Health Savings Account

• Tuition Reimbursement

• Ability to Participate in Employee Stock Purchase Program (ESPP)

• Mental Wellness Benefits through Spring Health

• Family-Forming support provided by Carrot

• Paid Parental Leave

• Flexible, full-service childcare support with Kinside

• 401(k) with a generous employer match

• Flexible PTO

• Catered lunch each day in our office and data center locations

• A casual work environment

• A work culture focused on innovative disruption

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. You can define and executing a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.

What You’ll Be Doing:

Defining and developing ASIC RTL design and verification at both chip and block levels. Creating and executing design plans for complex digital designs, particularly focusing on DDR, PCIe,CXL,UAL, UCIe IO protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced design and verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables.

The Impact You Will Have:

Enhancing the reliability and performance of Synopsys’ digital design processes. Driving innovations in DDR, PCIe, UAL, UCIe technology, contributing to the development of cutting-edge semiconductor solutions. Improving time-to-market for high-performance silicon chips through efficient methodologies. Building and nurturing a highly skilled development team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys’ capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.

What You’ll Need:

Extensive experience in ASIC RTL design. In-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications. Proficiency in advanced digital design tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams.

Who You Are:

A visionary leader with a strategic mindset. A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on advancing Synopsys' design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

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We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 5+ years or MSEE with 3+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.

You are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.

What You’ll Be Doing: Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies. Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements. Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities. Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics. Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure. Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity. Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

The Impact You Will Have: Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets. Drive innovation in verification methodologies, setting new standards for efficiency and coverage. Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle. Strengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus. Mentor and support junior engineers, fostering a culture of learning and continuous improvement. Contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.

What You’ll Need: BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification. Expertise in developing HVL (System Verilog)-based verification environments and testbenches. Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools. Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable. Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB. Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus. Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.

Who You Are: Analytical thinker with strong problem-solving and debugging skills. Excellent verbal and written communication abilities. Team player who thrives in collaborative, multi-site environments. Proactive, self-motivated, and able to take initiative on challenging projects. Detail-oriented, quality-focused, and driven by a desire to excel. Adaptable and eager to continuously learn and apply new technologies.

The Team You’ll Be A Part Of: You will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

A peek inside our office

Benefits: At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

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Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.

Responsibilities:

• Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.
• Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.

Requirements:

• Minimum 5+ years of experience in IP/ASIC/SOC design implementation.
• Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.
• Good communication skills while interacting with internal teams and customers.

Preferred Experience:

• Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.
• Experience in DesignWare Core IPs or PHYs.
• Experience in TCL, Perl, Python, or other shell scripting.

Benefits:

• Competitive salary and benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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The role involves leading the complete subsystem lifecycle,from requirements gathering and architecture definition to final release phases. This includes crafting subsystem architectures, developing comprehensive functional specifications, defining and implementing micro-architectures, and driving RTL quality checks.

The ideal candidate will have a minimum of 8 years of hands-on experience in RTL design and subsystem architecture for complex ASIC/SoC projects. They should be proficient with standard protocols including PCIe, DDR, UFS, USB, and AMBA, and have demonstrated expertise in low power design methodologies and DFT architecture.

As a leader, the candidate will inspire and guide their peers, leveraging their experience to drive innovation, efficiency, and reliability. They should be committed to continuous learning, open to new perspectives, and value an inclusive workplace where ideas from all backgrounds contribute to groundbreaking solutions.

The role offers a comprehensive range of health, wellness, and financial benefits to cater to the needs of the employee. The total rewards include both monetary and non-monetary offerings.

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As a Sr. Staff Engineer, you will be a key member of our Emulation/Validation team, responsible for bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.

Key responsibilities include:

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.
• Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.
• Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement.

The impact you will have includes enhancing cross-functional collaboration to elevate product quality and end-customer satisfaction, transforming the approach to Emulation IP usage in validating cutting-edge digital designs and system architectures, and driving innovation by defining and refining requirements for IP product development, particularly in emulation contexts.

To succeed in this role, you will need 8+ years of relevant experience in emulation, verification, or IP product development, expert-level knowledge of PCIe/ DDR/ Ethernet interfaces, including protocol and verification strategies, extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification, and a demonstrated track record in leading IP product development initiatives with a focus on emulation.

If you are a proactive and collaborative problem-solver with a passion for excellence, innovative thinker who embraces change and seeks out opportunities for continuous improvement, strong communicator able to articulate complex technical concepts to diverse audiences, resilient and adaptable, thriving in dynamic environments and embracing new challenges, and committed to mentoring others and fostering an inclusive, team-oriented culture, then we encourage you to apply for this exciting opportunity.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as HBM, DDR, PCIe/CXL, AMBA and its applications. You can define and execute a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.

What You’ll Be Doing:

• Defining and developing ASIC RTL design and verification at both chip and block levels.
• Creating and executing design plans for complex digital designs, particularly focusing on HBM, PCIe/CXL and AMBA protocols.
• Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.
• Utilizing advanced design and verification methodologies and tools to achieve high-quality results.
• Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.
• Communicating with internal and external stakeholders to align on project goals and deliverables.

The Impact You Will Have:

• Enhancing the reliability and performance of Synopsys’ digital design processes.
• Driving innovations in HBM, PCIe/CXL and AMBA technology, contributing to the development of cutting-edge semiconductor solutions.
• Improving time-to-market for high-performance silicon chips through efficient methodologies.
• Building and nurturing a highly skilled development team, elevating overall project quality.
• Influencing strategic decisions that shape the future of Synopsys’ capabilities.
• Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.

What You’ll Need:

• Extensive experience in ASIC RTL design.
• In-depth knowledge of HBM, PCIe, CXL, AMBA and similar IO protocols and their applications.
• Proficiency in advanced digital design tools and methodologies.
• Strong problem-solving skills and the ability to work independently.
• Excellent communication skills for effective collaboration with diverse teams.

Who You Are:

• A visionary leader with a strategic mindset.
• A mentor who fosters talent and encourages innovation.
• A proactive problem solver who thrives in complex environments.
• An effective communicator with the ability to convey technical concepts to a broad audience.
• A team player who values collaboration and diversity.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on advancing Synopsys' design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Staff ASIC Digital Design Engineer, you will be part of our R&D Professional team, specializing in mixed-signal ASIC development and supporting HBM/DDR PHY IP customers. You will work with experts in design, implementation, and verification.

Key responsibilities include:

Creating and debugging test benches and test cases Running RTL and gate-level simulations Supporting application engineers and customers on HBM/DDR PHY topics Contributing to technical documentation Driving product improvements based on customer feedback

The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:

ASIC RTL design and verification experience Verilog, PERL, TCL, Python skills Static timing analysis and synthesis knowledge Simulation and debugging abilities HBM/DDR protocol experience is an asset

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and perks during the hiring process.

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As a Senior Manager, ASIC Digital Design, you will lead a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions. You will collaborate with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.

Key responsibilities include:

• Leading a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions
• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products
• Planning, scheduling, and driving all phases of SERDES PHY IP design, from specification through productization and customer support
• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles
• Mentoring and developing team members, fostering technical growth, and a culture of innovation
• Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges

The impact you will have includes delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency, empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications, and driving technical innovation that strengthens Synopsys' leadership in the mixed-signal IP market.

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ASIC/SoC Presales Applications Engineer - 16648

Sunnyvale, California, United States

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Category: EngineeringHire Type: Employee

Job ID 16648Base Salary Range $184000-$276000Date posted 03/31/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned ASIC, SoC, or Chiplet Architect, Manager, or Design Engineer, bringing extensive expertise in IC Digital, Mixed Signal, or Analog Design. Your technical prowess is matched by your ability to engage and inspire customers, translating complex engineering concepts into clear, impactful solutions. You thrive in fast-paced, dynamic environments and are adept at navigating competitive landscapes. Your organizational skills and self-motivation ensure you deliver on ambitious goals, while your creative approach to problem-solving enables you to overcome challenges with finesse. You build trust and rapport quickly, fostering long-lasting relationships with both internal teams and external stakeholders. With a Bachelor’s (15+ years) or Master’s (11+ years) degree in a relevant field, you understand industry protocols such as SerDes, UCIe, PCIe, DDR, USB, MIPI, or Ethernet, bringing added value to each engagement. You are passionate about driving technology forward and contributing to customer success, ready to make a significant impact at Synopsys.

What You’ll Be Doing:

• Presenting Synopsys solutions to senior managers and technical stakeholders, showcasing the value and capabilities of our IP portfolio.

• Engaging with customers to understand their unique requirements and challenges, proposing tailored technical solutions that meet their needs.

• Positioning Synopsys competitively in technical discussions, articulating differentiators and advantages in the marketplace.

• Liaising between technical, marketing, and sales teams to ensure seamless communication and alignment on project objectives.

• Driving strategy and execution for technical solution design, influencing customer architectures and product adoption.

• Supporting sales and business unit negotiations with expert insight into technical feasibility, solution fit, and value proposition.

The Impact You Will Have:

• Lead customer engagements, ensuring Synopsys solutions align perfectly with client requirements and goals.

• Collaborate across global teams to deliver innovative, winning solutions that drive business growth.

• Accelerate adoption of Synopsys products and platforms within key customer accounts.

• Provide critical technical insight, shaping the design and success of customer chip projects.

• Drive customer and business success by enabling efficient, high-performance SoC and ASIC design.

• Ensure successful delivery of complex SoC projects across multiple regions, supporting Synopsys' reputation as a market leader.

What You’ll Need:

• Deep expertise in IC design, including Digital, Mixed Signal, or Analog domains.

• Experience in customer-facing roles, technical sales, or sales support within the semiconductor industry.

• Exceptional communication skills, able to convey complex technical concepts to diverse audiences.

• Strong organizational and project management abilities, driving multiple projects to completion.

• Solid understanding of major semiconductor IP product lines and industry protocols (SerDes, UCIe, PCIe, DDR, USB, MIPI, Ethernet).

Who You Are:

A creative problem solver and strategic thinker, you excel at collaborating with diverse teams and stakeholders. You are driven by a passion for technology, innovation, and customer success, bringing a positive, solutions-oriented mindset to every challenge. Your adaptability and leadership enable you to thrive in high-pressure situations, while your integrity and commitment build trust across all levels of the organization.

The Team You’ll Be A Part Of:

You’ll join a collaborative group dedicated to delivering groundbreaking chip design solutions using Synopsys IP. The team works closely with Sales, R&D, and Marketing, fostering a supportive and innovative environment where your ideas and expertise will help shape next-generation semiconductor products.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

As a Senior ASIC Physical Design Engineer, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).

You will drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.

You will collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.

You will integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.

You will design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.

You will participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.

You will support the implementation of best practices in floorplanning, placement, routing, and power optimization.

You will mentor junior engineers and contribute to team knowledge sharing initiatives.

Impact

You will enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.

You will advance Synopsys' leadership in IP implementation at cutting-edge technology nodes.

You will champion best-in-class timing closure and integration practices, raising the bar for design excellence.

You will facilitate seamless cross-site collaboration, ensuring global project success.

You will drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.

You will accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.

Requirements

Bachelor's or Master's degree in Electronics, Electrical Engineering, or related field.

3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).

Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).

Solid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.

Experience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.

Familiarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.

Strong analytical and debugging skills for addressing complex design challenges.

Team

You will join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology.

The team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals.

Together, you will help shape the future of high-performance silicon and enable the next wave of intelligent systems.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You will report key metrics and drive continuous improvement initiatives in Emulation IP quality and performance.

You will provide technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.

You will stay ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.

You will review and validate test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.

You will collaborate cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.

You will mentor and guide junior engineers, fostering a culture of innovation and continuous improvement.

This role requires 10-20 years of relevant experience in emulation, verification, or IP product development.

You should have expert-level knowledge of PCIe and DDR interfaces, including protocol and verification strategies.

You should have extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

You should have demonstrated track record in leading IP product development initiatives with a focus on emulation.

You should have strong background in cross-functional collaboration, with an ability to drive consensus and deliver results.

You should have outstanding communication skills, with the ability to influence and inspire change across diverse teams.

You should be adaptable and comfortable working in a fast-paced, matrixed, and international environment.

As a proactive and collaborative problem-solver with a passion for excellence, you will be a strong fit for this role.

You will join a dynamic, high-performing engineering team focused on IP development, emulation, and verification at the forefront of semiconductor innovation.

Our team is collaborative, cross-functional, and globally distributed, working together to solve complex challenges and deliver industry-leading solutions.

You will have the opportunity to collaborate with experts across multiple domains, drive impactful initiatives, and shape the future of digital design and verification at Synopsys.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

13752

Remote Eligible

No

Date Posted

12/16/2025

Responsibilities

• Reviewing Die, package, and PCB physical layout designs
• Modelling, simulating, and verifying high-speed interface performance against specifications
• Participating in the improvement of SI/PI methodology flows
• Collaborating and networking with other teams on task-oriented projects
• Independently driving SI/PI research and development activities

Impact

• Enabling SI/PI sign-off of high-speed interfaces for various Customer SoC/PKG/PCB designs targetting different applications
• Improve SI/PI methodology flows, increasing efficiency and accuracy
• Foster collaboration and innovation across globally distributed teams
• Drive research and development initiatives of next gen IP's (MRDIMM, LPDDR6, HBM4, UCIE) to stay ahead in the industry and offer guidance to our customers
• Support Synopsys' mission to lead in the Era of Pervasive Intelligence

Requirements

• Bachelor's or Master's degree in Electrical or Electronics Engineering
• Minimum of 8 years of relevant experience
• Proficient in Transmission line theory and time/frequency-domain analysis
• Experienced with SPICE and familiar with 3D field solvers
• Conversant with working of DDR, HBM, UCIE and PCIe/Ethernet interfaces
• Good verbal and written English communication skills
• Experience in scripting languages such as Python and TCL is a plus
• Familiarity with both Windows and Linux operating systems

Who You Are

You are a proactive and innovative engineer who thrives in a collaborative environment. You have a strong technical background and excellent problem-solving skills. Your ability to communicate effectively and work well with diverse teams makes you an asset to any project. You are dedicated to continuous learning and development, and your passion for technology drives you to stay ahead of industry trends. You are adaptable, detail-oriented, and committed to delivering high-quality results.

Team

You will be working with a group of highly-skilled, supportive, and globally spread-out teams. Our team is dedicated to driving innovation and excellence in SIPI analysis of high speed interface IP's. We value collaboration, continuous learning, and a can-do attitude. Together, we strive to develop the most advanced technologies and deliver exceptional results for our clients.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.

Responsibilities

Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.

Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.

Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.

Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.

Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.

Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.

Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.

4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.

Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.

Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.

Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.

Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.

Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).

Exposure to quality processes in IP design and verification is an advantage.

Prior experience as a technical lead or mentor is highly desirable.

Who We Are Looking For

Innovative thinker with a solutions-oriented mindset and a passion for technology.

Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.

Natural leader with mentoring abilities, fostering inclusion and diversity within the team.

Detail-oriented professional with strong analytical and problem-solving skills.

Self-motivated, adaptable, and eager to drive technical excellence and process improvements.

Committed to continuous learning and staying ahead of industry trends.

The Team You’ll Be A Part Of

You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are seeking a highly skilled and experienced ASIC verification professional to lead technical teams and drive excellence in digital design.

As a Sr Staff Engineer - DDR, you will be responsible for technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.

You will specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores.

You will perform verification tasks for IP cores, working closely with RTL designers and architects to ensure functional correctness.

You will develop and implement advanced test plans and test environments at both unit and system levels.

You will code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.

You will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.

You will manage regressions and contribute to the continuous improvement of verification strategies and test environments.

This role requires a deep understanding of verification methodologies, serial interface protocols, and the intricacies of IP core development.

You should have demonstrated experience in technically leading a team for DDR IP projects, with a track record of successful collaboration and stakeholder management.

You should have proven expertise in developing HVL (System Verilog/UVM) based test environments for complex ASIC designs.

You should have advanced skills in developing and implementing rigorous test plans, checkers, and assertions.

You should have strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.

You should have experience with serial interface protocols and IP design/verification processes; knowledge of DDR/LPDDR is highly desirable.

You should have hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.

You will join the DesignWare IP Verification R&D team, a group of talented and passionate engineers committed to advancing Synopsys' leadership in semiconductor IP.

The team focuses on delivering world-class verification solutions for a broad portfolio of synthesizable IP cores, leveraging the latest methodologies and technologies to ensure our products meet the most rigorous quality and performance standards.

Collaboration, innovation, and a drive for excellence define our culture.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

XML job scraping automation by YubHub

They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted: 03/09/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.

You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.

With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.

Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.

What You’ll Be Doing:

• Lead and Drive all aspects of complete IP Design execution from start to end.

• Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.

• Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.

• Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.

• Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.

• Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.

• Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.

• Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.

The Impact You Will Have:

• Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.

• Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.

• Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.

• Enabling customers to achieve faster time-to-market and superior silicon performance.

• Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.

• Driving continuous improvement in design methodologies, enhancing efficiency and product quality.

• Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.

• 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.

• Past experience of leading IP deign projects, team.

• In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.

• Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.

• Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).

• Familiarity with scripting languages such as Perl or Shell—an advantage.

• Demonstrated ability to technically lead or mentor small teams of engineers.

Who You Are:

• A collaborative team player who thrives in a multi-site, multicultural environment.

• An effective communicator, able to translate complex technical concepts for diverse audiences.

• A proactive problem-solver with strong analytical and troubleshooting skills.

• Self-motivated, showing high initiative and ownership of responsibilities.

• Adaptable and eager to learn, always seeking opportunities for personal and professional growth.

• Committed to fostering a positive, inclusive, and innovative team culture.

The Team You’ll Be A Part Of:

You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.

As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.

The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world.

We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.

We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

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Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15159

Remote Eligible

No

Date Posted

02/04/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an enthusiastic and detail-oriented SoC RTL Performance Verification Engineer with a passion for developing and deploying verification solutions for System on Chip (SoC) designs. With a strong background in RTL hardware design and verification, you excel in using industry-standard languages like Verilog and SystemVerilog. Your expertise in developing ZeBu emulation-based verification IP (transactor) and solutions makes you a valuable asset to any team. You thrive in dynamic environments, tackling complex problems creatively while adhering to company policies and procedures. Your communication skills are exemplary, allowing you to work effectively with both internal teams and external clients. With a deep understanding of protocols like AMBA AXI/CHI and proficiency in UNIX and scripting, you bring a comprehensive skill set to the table, ready to make an impact in the rapidly evolving field of SoC performance verification.

What You’ll Be Doing:

• Developing SoC Performance Validation (PV) flow and components (transactor model and CI/CD automation) on ZeBu emulator.

• Creating emulation-based transactor and solutions using SystemVerilog and C++.

• Providing technical support and guidance to customers during the deployment of the ZeBu emulator.

The Impact You Will Have:

• Ensuring the reliability and performance of customer SoC designs through rigorous validation processes.

• Enhancing the capabilities of the ZeBu emulator transactor to meet evolving industry standards and customer needs.

• Contributing to the development of innovative SoC PV solutions that set Synopsys apart from competitors.

• Supporting customers in achieving their design and performance goals, thereby strengthening Synopsys' market position.

• Driving continuous improvement in SoC PV methodologies, leading to more efficient and effective processes.

• Fostering collaboration and knowledge sharing within the team, enhancing overall performance and innovation.

What You’ll Need:

• Bachelor's degree in Electrical Engineering or a related field (RTL design/verification) with a minimum of 12+ years of experience.

• A solid understanding of the SoC architecture among HW IPs, AMBA system buses, and LPDDR memory controllers in a mobile AP.

• Proficiency in developing emulation-based transactor models and solutions using SystemVerilog and C++.

• Proficiency with UNIX and scripting.

The Team You’ll Be A Part Of:

You will be part of a dynamic and innovative team focused on developing and deploying cutting-edge verification solutions for SoC designs. The team values collaboration, continuous learning, and a commitment to excellence, working together to drive technological advancements and deliver exceptional results for our customers.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a skilled and passionate engineer with expertise in system design, embedded firmware, digital design, and verification with over 8+ years of experience. You are a skilled engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry. You value collaboration and mentorship, welcoming opportunities to both learn from and share knowledge with your peers. Your experience with memory interface protocols such as DDR, LPDDR and HBM enables you to quickly contribute to our next-generation solutions.

Technical knowledge in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results. You are passionate about right first-time development, ensuring traceability of all verification requirements and covering the whole ecosystem of Controller and PHY.

You bring knowledge of system, digital, firmware design, high-speed memory interface skills. Your experience includes delivering "best-in-class" solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.

What You’ll Be Doing:

• Developing and optimizing embedded firmware for advanced DDR/LPDDR/HBM memory interface PHYs
• Contributing and collaborating with hardware teams to analyze and debug embedded firmware
• Optimizing and developing new PHY training algorithms using system level modeling tools
• Collaborating closely with analog, digital, and hardware teams to ensure overall system integrity
• Bridging the gap between pre- and post-silicon verification to ensure best-in-class customer support
• Developing and deploying tests on silicon as part of bring up plan with extensive knowledge of the design internals
• Reproducing silicon failures on FPGA/Emulation to identify root causes
• Fostering technical excellence and knowledge sharing across the organization.

The Impact You Will Have:

• Enhancing cross-functional collaboration to improve product quality and end customer satisfaction.
• Evolving/adopting and integrating best-in-class methodologies within the organization for fast silicon bring-up
• Standardizing and optimizing workflows to increase efficiency and compliance.
• Accelerating product innovation and time-to-market by establishing best practices to bridge the gap between architecture and physical implementation using system modeling, functional simulation emulation, and system integration.
• Directly impact customer success by providing guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

What You’ll Need:

• 8+ years of experience in Firmware, ASIC design, verification, system validation, and technical roles.
• Be results driven
• Proven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.
• Advanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.
• In-depth knowledge of system-level validation for high-speed interface PHY
• Proven track record of working cross-functionally and driving issues to closure
• Knowledge of mixed-signal design
• Experience in working in cross-functional collaborations
• Be an excellent communicator and a beacon for change

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity:

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

XML job scraping automation by YubHub

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk.

You Are:

You are a talented Firmware Development Engineer with a passion for embedded systems and software innovation. You thrive in environments where high-speed and precision matter, bringing a strong programming background and an aptitude for developing reliable, scalable firmware solutions. Your expertise in C programming and familiarity with scripting languages such as Perl, TCL, or Python make you a versatile contributor. You are experienced in developing firmware for complex embedded systems and high-speed interfaces, and you take pride in rigorous problem-solving and debugging. You enjoy collaborating with hardware engineers to ensure seamless integration between firmware and hardware, and you are skilled at navigating verification and emulation environments to enhance product quality. Your attention to detail and commitment to delivering robust, high-quality firmware are matched by your ability to adapt to new challenges in a fast-moving industry. You value diversity and inclusion, and you are comfortable working in a dynamic, multicultural team. Whether you are mentoring junior engineers, spearheading integration efforts, or contributing to pre-silicon environments, you consistently demonstrate initiative, innovation, and a collaborative spirit. If you are excited to power the Era of Smart Everything and help shape tomorrow’s breakthroughs, you’ll find your place at Synopsys.

What You’ll Be Doing:

• Designing and implementing firmware for high-speed PHY IPs using C programming.
• Developing and maintaining software development environments and tools to streamline workflows.
• Collaborating with hardware engineers to ensure firmware compatibility and optimized integration with hardware designs.
• Conducting rigorous unit testing and debugging to ensure high-quality firmware performance
• Utilizing verification and emulation environments to enhance the integration process and support pre-silicon development.
• Documenting design processes, maintaining code quality, and ensuring compliance with industry standards.
• Staying current with emerging technologies in embedded systems and high-speed interfaces.

The Impact You Will Have:

• Accelerating the integration of advanced capabilities into SoCs through robust firmware development.
• Enhancing product reliability, performance, and time-to-market for customers in diverse industries.
• Supporting the development of differentiated products that power innovations like AI, 5G, IoT, and self-driving cars.
• Reducing risk and optimizing project outcomes by leveraging your expertise in embedded systems and high-speed interfaces.
• Driving cross-functional collaboration between software and hardware teams to deliver seamless solutions.
• Contributing to Synopsys’ leadership in silicon IP and embedded technology by delivering high-quality, scalable firmware.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Strong programming skills in C and familiarity with software development methodologies.
• Experience with scripting languages such as Perl, TCL, or Python.
• Proven experience in firmware development for complex embedded systems or high-speed interfaces.
• Excellent problem-solving and debugging skills, especially in unit testing and integration scenarios.
• Knowledge of high-speed interface protocols such as DDR, LPDDR (preferred).
• Experience with pre-silicon environments, including verification or emulation (preferred).

Who You Are:

• Analytical, detail-oriented, and committed to delivering high-quality results.
• Collaborative and effective communicator, able to work across diverse teams and disciplines.
• Adaptable and eager to learn new technologies and methodologies.
• Proactive, with a passion for innovation and continuous improvement.
• Inclusive and respectful, supporting a diverse and multicultural work environment.

The Team You’ll Be A Part Of:

You will join a vibrant Silicon IP engineering team dedicated to developing and integrating advanced firmware for high-speed interfaces. The team consists of experts in embedded systems, software, and hardware design, working together to solve complex challenges and deliver industry-leading solutions. Collaboration, innovation, and a commitment to excellence define the team’s culture as they support customers in bringing differentiated products to market quickly and efficiently.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted 02/24/2026

Category EngineeringHire Type EmployeeJob ID 15312Remote Eligible NoDate Posted 02/24/2026

Senior Digital Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an ambitious and detail-oriented engineering professional with a passion for digital verification and ASIC design. You thrive in dynamic and diverse environments, bringing a collaborative spirit and a strong eagerness to learn. Your background in electronics engineering equips you with deep technical expertise, and your experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs sets you apart. You approach challenges with a solution-oriented mindset and are adept at diagnosing intricate issues efficiently. You are comfortable working across multiple verification platforms and methodologies, and you enjoy mentoring and sharing knowledge within your team. Your adaptability enables you to keep pace with evolving technologies, and you value inclusion, diversity, and continuous improvement. You are motivated by the opportunity to contribute to groundbreaking innovations in the silicon IP domain, and you are committed to delivering quality results that help bring differentiated products to market quickly. If you are excited by the chance to be at the forefront of smart technology—powering everything from AI to IoT—you will find your next challenge here at Synopsys.

What You’ll Be Doing:

• Developing robust functional verification environments (test benches) for high-speed PHY IPs.
• Creating comprehensive test plans and detailed test cases to ensure thorough coverage.
• Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs).
• Executing simulations, generating both random and focused stimuli, and performing coverage analysis to validate design functionality.
• Building architectural and micro-architectural understanding of complex digital design blocks under verification.
• Collaborating with cross-functional engineering teams to resolve issues and optimize verification strategies.
• Contributing to process improvements and sharing best practices within the team.

The Impact You Will Have:

• Accelerate the integration of advanced capabilities into SoCs, enabling customers to meet performance, power, and size requirements.
• Ensure the delivery of differentiated, high-quality silicon IP products with reduced risk and faster time-to-market.
• Drive innovation in verification methodologies that support the development of next-generation technologies, including AI, cloud, 5G, and IoT.
• Enhance the reliability and functionality of high-speed digital interfaces, powering smart devices across industries.
• Support Synopsys’ leadership in chip design and software security by maintaining rigorous verification standards.
• Contribute to a culture of inclusion and excellence, mentoring junior engineers and promoting diversity within the team.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Solid background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs.
• Proficiency in Verilog, System Verilog, UVM, and netlist simulations.
• Experience with industry-standard development and verification tools and methodologies.
• Excellent diagnostic and problem-solving skills for identifying and resolving verification issues.
• Preferred: Experience with formal verification, System Verilog Assertions, and code/functional coverage implementation and analysis.
• Preferred: Familiarity with scripting languages such as Perl, TCL, and Shell scripting.
• Preferred: Knowledge of high-speed interface protocols such as DDR and LPDDR.

Who You Are:

• Detail-oriented and analytical thinker with a proactive approach to problem-solving.
• Effective communicator who thrives in collaborative and diverse team environments.
• Adaptable and eager to learn new technologies and methodologies.
• Resourceful and resilient in overcoming technical challenges.
• Committed to fostering inclusion, respect, and continuous improvement within the workplace.

The Team You’ll Be A Part Of:

You will join a high-performing Silicon IP engineering team that specializes in developing and verifying advanced digital design blocks for integration into SoCs. Our team values innovation, collaboration, and knowledge sharing, working together to deliver industry-leading solutions for customers worldwide. We are passionate about technology and driven by the success of our products and people.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

A peek inside our office

Po Popal

Workplace Resources, Sr Director

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Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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You are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with EM and IR flows. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.

Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

You will develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. You will work with leading edge designs and teams to drive the industry best PPA for IP designs. You will evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO's.

You will develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. You will work as a liaison between EDAG tool and IP design teams. You will continuously improve and refine design processes to enhance efficiency and performance.

You will have a BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.

You will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.

You will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

You will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.

You will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.

You will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What are we looking for?

We're looking for a PE Agent with excellent communication skills, flexibility to adapt to various situations and player needs, and accountability and reliability in handling player inquiries and issues. You should have mastery in C1-C2 level language proficiency, with English at B2 level or higher, and experience in supporting a live chat environment.

Responsibilities:

• Deliver excellent customer support to players
• Investigate and resolve player inquiries promptly through ticketing, email, or chat
• Assist internal teams with project-related requests, ensuring smooth collaboration
• Play a crucial role in gathering and delivering player feedback according to established procedures
• Provide translations when required to ensure seamless communication
• Maintain accurate and detailed reports to keep processes streamlined
• Ensure prompt escalation of issues following established procedures
• Contribute to smoother support processes with personalized macros and knowledge base
• Play a part in maintaining high-quality standards through the QC process

Requirements:

• Mastery in C1-C2 level language proficiency, with English at B2 level or higher
• Excellent communication skills for effective player support
• Flexibility to adapt to various situations and player needs
• Accountability and reliability in handling player inquiries and issues
• Proactivity in identifying and addressing player concerns proactively
• Proficiency in navigating knowledge bases for efficient support
• Basic troubleshooting skills to assist players with technical challenges
• Availability for full-time work, including weekends and holidays, and on different time zones as needed
• Able to work onsite for an indefinite period (role will eventually transition to WFH)
• Previous BPO experience supporting a live chat environment (plus if you have experience handling 3 chat concurrencies) - must have!
• You have some knowledge of the community platforms (e.g. Discord, Slack) - this could be an asset.
• Familiarity in PC and console platforms is an advantage!

Benefits:

• Non-taxable Allowances
• HMO and Life Insurance
• Paid Time Offs
• Annual Wellness Subsidy

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As a Player Engagement Agent, you'll serve as the essential link between our clients and the gaming community. Your responsibilities include investigating and delivering prompt, quality responses to players' questions while providing valuable feedback to our developers.

What We're Looking For

Our PE Agent has a knack for the following skills:

• Communication: Deliver excellent customer support to players, investigate and resolve player inquiries promptly through ticketing, email, or chat, assist internal teams with project-related requests, ensuring smooth collaboration, play a crucial role in gathering and delivering player feedback according to established procedures, and provide translations when required to ensure seamless communication.

• Analytics: Maintain accurate and detailed reports to keep processes streamlined, ensure prompt escalation of issues following established procedures, contribute to smoother support processes with personalized macros and knowledge base, and play a part in maintaining high-quality standards through the QC process.

• Leadership: Take part in valuable training sessions to enhance your skills and knowledge, manage your time effectively and responsibly to meet players' needs.

Requirements

You'd be a great fit for this role if you have:

• Mastery in C1-C2 level language proficiency, with English at B2 level or higher.

• Excellent communication skills for effective player support.

• Flexibility to adapt to various situations and player needs.

• Accountability and reliability in handling player inquiries and issues.

• Proactivity in identifying and addressing player concerns proactively.

• Proficiency in navigating knowledge bases for efficient support.

• Basic troubleshooting skills to assist players with technical challenges.

Benefits

Keywords Studios is dedicated to following a well-established Equal Opportunities Policy. We endeavor to create a workplace which provides equal opportunities for all employees and potential employees. Helpshift embraces diversity. We are proud to be an equal opportunity workplace and do not discriminate on the basis of sex, race, color, age, sexual orientation, gender identity, religion, national origin, citizenship, marital status, veteran status, or disability status.

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San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Legal

Compensation

• $248K – $275K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI's Legal team plays a crucial role in furthering OpenAI's mission by tackling innovative, fundamental legal issues in AI. If you're passionate about doing significant and unique work as a technology lawyer, this team is for you. The team comprises professionals from diverse fields, including technology, AI, privacy, IP, corporate, employment, tax law, regulatory, and litigation.

About the Role

As a member of our AI Product Counsel team focusing on research, you will assist with legal initiatives related to our advanced AI models and technologies. You’ll partner closely with researchers and engineers to help them plan, develop, and align models such as GPT-5, as well as our future research roadmap. This is a unique opportunity to engage directly with the forefront of the legal and AI fields. This role reports to our lead counsel for AI Research.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role, you will:

• Be the go-to counsel and partner for several research teams focused on AI research and model development.
• Identify and address copyright, regulatory, privacy, and other legal risks and mitigations related to AI model development and deployment.
• Develop strategies for handling legal issues in creative ways and build processes for scaling flexible solutions that address risk.
• Become an expert in AI legal matters and help propose and advance AI legal policy positions.

You’ll enjoy this role if you:

• Have a JD and license or qualification to practice in CA.
• Have 5+ years of experience with a mix of in-house and technology-focused law firm roles, including significant copyright experience.
• Understand the letter of the law and can approach problems in a practical, principled approach.
• Build cross-functional relationships and communication styles that resonate with teams to balance risk-taking with responsible development.
• Have a strong sense of ownership, are inquisitive and enthusiastic about technology, enjoy being continually challenged, and can demonstrate sound judgment in ambiguous situations.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.

What you need

• 8+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe or DDR interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

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What you'll do

• Leading and managing a team of ASIC Digital Verification engineers, providing guidance and mentorship;
• Creating and maintaining testbenches using SystemVerilog and UVM methodologies;

What you need

• Extensive experience in ASIC digital verification, particularly with HBM (or DDR/LPDDR) protocols;
• Proficiency in SystemVerilog, UVM, and other verification tools and methodologies;

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What you'll do

As a Sr Staff Engineer, you will be responsible for designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.

• Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.
• Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.
• Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.

What you need

• MS/PhD in Computer Science, Electrical Engineering, or related field from a reputed institute, with 10+ years of relevant experience.
• Expertise in RTL development using Verilog or System Verilog, with a strong background in digital design principles.
• Hands-on experience with Xilinx and Altera FPGA platforms, including familiarity with Xilinx Vivado and related tools.
• Advanced problem-solving and debugging skills, especially in digital verification, emulation, and prototyping environments.
• Experience with scripting languages such as Tcl, Python, Perl, and a solid understanding of system and CPU architecture (DMA, interrupts, etc.).
• Exposure to embedded system development and interface protocols (USB, PCIe, DDR, AXI).

Why this matters

• Accelerate the development of industry-leading prototyping systems, enabling faster time-to-market for cutting-edge ASIC designs.
• Enhance the functionality and reliability of Synopsys' HAPS and ProtoCompiler products through innovative hardware and software solutions.
• Drive customer satisfaction by delivering robust, scalable, and user-friendly prototyping tools that meet diverse engineering needs.
• Contribute to Synopsys' reputation as a leader in verification and prototyping technology, influencing industry standards and practices.

What you'll be doing

• Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.
• Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.
• Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.
• Developing and maintaining complex EDA software for high-performance prototyping systems.
• Implementing digital debug, verification, emulation, and prototyping strategies to ensure robust and reliable designs.
• Creating RTL for interfaces such as USB, PCIe, DDR, and AXI, and overseeing full design flow including verification and lab bring-up.
• Supporting and enhancing existing products and features, responding to evolving customer needs with innovative solutions.
• Exploring and implementing new approaches to address current and future challenges, continuously learning and applying new technologies.
• Mentoring junior engineers, providing guidance and support to foster growth and technical excellence within the team.
• Collaborating independently and within cross-functional teams, networking with senior internal and external stakeholders.

Why you'll love this role

• Opportunity to work on cutting-edge projects and technologies.
• Collaborative and dynamic work environment.
• Professional growth and development opportunities.
• Recognition and rewards for outstanding performance.
• Comprehensive benefits and compensation package.

What you'll need to succeed

• Strong technical skills and knowledge in digital design, verification, and prototyping.
• Excellent problem-solving and debugging skills.
• Strong communication and collaboration skills.
• Ability to work independently and as part of a team.
• Adaptability and flexibility in a fast-paced environment.

How to apply

• If you're ready to make a meaningful impact and help shape the next generation of prototyping systems, Synopsys is the place for you.
• Apply now to join our team of talented engineers and contribute to the development of industry-leading prototyping solutions.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• Time away, including company holidays, ETO, and FTO programs.
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
• ESPP, with a 15% discount on Synopsys common stock.
• Retirement plans, varying by region and country.
• Competitive salaries.

How we hire

• We're proud to be an equal opportunities employer and welcome applications from diverse candidates.
• Our hiring process typically involves a phone screen, followed by an interview with the hiring team.
• We're committed to providing a supportive and inclusive work environment, where everyone has the opportunity to grow and succeed.

Join our team

• If you're passionate about innovation and technology, and want to be part of a dynamic and collaborative team, apply now to join Synopsys.
• We can't wait to hear from you!

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What you'll do

You will be responsible for designing and developing cutting-edge semiconductor solutions. You will work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

• Implement and integrate state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).
• Drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.

What you need

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field.
• 3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).
• Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).

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What you'll do

• Developing and writing high-quality user documentation for a variety of Digital and Mixed Signal IPs, including USB, PCIe, Ethernet, DDR, HDMI, and MIPI.
• Planning, organizing, and editing technical specifications, engineering schematics, application notes, and user guides to ensure clarity and usability.

What you need

• Bachelor’s or Master’s degree in Electronics, Science, Hardware, Computing, Software, Physics, Mathematics, Engineering, or a related technical discipline.
• 3-7 years of technical writing experience in the software or hardware industry, with proven ability to deliver high-quality documentation.

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What you'll do

Develop a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys' best in class tools and technologies.

Work with leading edge designs and teams to drive the industry best PPA for IP designs.

Evaluate and exercise various aspects of the development flow which may include design for test logic, synthesis, place & route, timing and power (incl. EM/IR) optimization and analysis.

Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.

Work as a liaison between EDAG tool and IP design teams.

Continuously improve and refine design processes to enhance efficiency and performance.

What you need

BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.

Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.

Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools.

Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.

Good analysis, debugging, and problem-solving skills.

Solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.

Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) is a plus.

Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

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What you'll do

You will be responsible for developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.

• Translating architectural requirements and industry standard specifications into robust, high-performance RTL implementations using SystemVerilog and Verilog.

What you need

• 7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.

Why this matters

Drive the development of cutting-edge HBM PHY IP, enabling industry-leading memory bandwidth for next-generation computing systems.

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What you'll do

• Lead the design and development of high-speed IO, DDR, and HBM interfaces.
• Collaborate with cross-functional teams to drive innovation and deliver high-quality products.
• Develop and maintain technical documentation and presentations.

What you need

• Bachelor's degree in Electrical Engineering or Computer Science.
• 10+ years of experience in analog and mixed-signal design.
• Strong understanding of analog IC architecture and transistor-level circuit design.
• Excellent communication and leadership skills.

Why this matters

• Enhance team efficiency and influence product strategy.
• Deliver innovative solutions that shape the future of semiconductor technology.
• Make a significant impact and drive business growth.

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What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.

What you need

• 8+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe/ DDR/ Ethernet interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

XML job scraping automation by YubHub

What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.

What you need

• 15+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe/ DDR / Ethernet interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

XML job scraping automation by YubHub

What you'll do

Specifying, designing, and implementing state-of-the-art verification environments for the DesignWare family of synthesizable cores.

Performing verification tasks for IP cores, including test planning and environment coding at both unit and system levels.

Developing and implementing test cases, debugging, functional coverage coding, and testing to meet quality metric goals.

Managing regression and ensuring adherence to verification methodologies.

Collaborating closely with RTL designers and a global team of verification engineers.

Working on next-generation connectivity protocols for commercial, enterprise, and automotive applications.

What you need

BSEE in Electrical Engineering with 12+ years of relevant experience or MSEE with 10+ years of relevant experience.

Experience in architecting verification environments for complex serial protocols.

Proficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI.

Expertise in verification methodologies such as VMM, OVM, and UVM.

Knowledge of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB.

Familiarity with Verilog and scripting languages such as Perl, TCL, and Python.

Experience with IP design and verification processes, including VIP development.

XML job scraping automation by YubHub

What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.

What you need

• 15+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe/ DDR / Ethernet interfaces, including protocol and verification strategies.

XML job scraping automation by YubHub

What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.
• Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.
• Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement.

What you need

• 8+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe or DDR interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.
• Demonstrated track record in leading IP product development initiatives with a focus on emulation.
• Strong background in cross-functional collaboration, with an ability to drive consensus and deliver results.
• Outstanding communication skills, with the ability to influence and inspire change across diverse teams.
• Adaptability and comfort working in a fast-paced, matrixed, and international environment.

XML job scraping automation by YubHub