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      <externalid>e9f309b8-35d</externalid>
      <Title>Senior Manager, ASIC Digital Design</Title>
      <Description><![CDATA[<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>
<p>As a Senior Manager, ASIC Digital Design, you will lead a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions. You will collaborate with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.</p>
<p>Key responsibilities include:</p>
<ul>
<li>Leading a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions</li>
<li>Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products</li>
<li>Planning, scheduling, and driving all phases of SERDES PHY IP design, from specification through productization and customer support</li>
<li>Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles</li>
<li>Mentoring and developing team members, fostering technical growth, and a culture of innovation</li>
<li>Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges</li>
</ul>
<p>The impact you will have includes delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency, empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications, and driving technical innovation that strengthens Synopsys&#39; leadership in the mixed-signal IP market.</p>
<p style="margin-top:24px;font-size:13px;color:#666;">XML job scraping automation by <a href="https://yubhub.co">YubHub</a></p>]]></Description>
      <Jobtype>full-time</Jobtype>
      <Experiencelevel>senior</Experiencelevel>
      <Workarrangement>onsite</Workarrangement>
      <Salaryrange></Salaryrange>
      <Skills>Verilog, System Verilog, front-end design flows, linting, synthesis, static timing analysis, cross-domain clocking, DFT, power optimization, DDR memory, DDR PHY architecture</Skills>
      <Category>Engineering</Category>
      <Industry>Technology</Industry>
      <Employername>Synopsys</Employername>
      <Employerlogo>https://logos.yubhub.co/careers.synopsys.com.png</Employerlogo>
      <Employerdescription>Synopsys is a leading provider of electronic design automation (EDA) software and services. It is a multinational corporation headquartered in Mountain View, California.</Employerdescription>
      <Employerwebsite>https://careers.synopsys.com</Employerwebsite>
      <Compensationcurrency></Compensationcurrency>
      <Compensationmin></Compensationmin>
      <Compensationmax></Compensationmax>
      <Applyto>https://careers.synopsys.com/job/kanata/senior-manager-asic-digital-design/44408/93286401664</Applyto>
      <Location>Kanata</Location>
      <Country></Country>
      <Postedate>2026-04-05</Postedate>
    </job>
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