{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/ddr-hbm-hbi-ip-integration"},"x-facet":{"type":"skill","slug":"ddr-hbm-hbi-ip-integration","display":"DDR/HBM/HBI IP integration","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cd352346-abd"},"title":"ASIC Physical Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutionsΈ. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly skilled ASIC Physical Design Staff Engineer to join our team. As a Staff Engineer, you will be responsible for implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes, ensuring world-class performance and quality. You will also drive timing closure efforts, especially above ~2GHz, and resolve complex challenges related to mixed signal and macro IP integration.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes</li>\n<li>Driving timing closure efforts, especially above ~2GHz</li>\n<li>Resolving complex challenges related to mixed signal and macro IP integration</li>\n<li>Designing and optimizing clock trees with tight skew balancing to meet stringent performance requirements</li>\n<li>Collaborating daily with local and US counterparts, contributing to technical discussions, and sharing best practices across teams</li>\n<li>Leading project tasks independently, providing regular updates to management, and representing the organization in business unit and company-wide projects</li>\n<li>Mentoring junior engineers, guiding them through technical challenges, and fostering a culture of continuous learning and innovation</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum 6 years of experience in ASIC physical design, preferably with post-graduate qualifications</li>\n<li>Expertise in tools such as Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), and Formality (FC)</li>\n<li>Proven experience with DDR/HBM/HBI timing closure, implementation, and IP integration</li>\n<li>Strong analytical and problem-solving skills, with a track record of resolving complex technical issues</li>\n<li>Ability to independently lead project tasks, mentor junior team members, and work collaboratively</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans</li>\n<li>Time away from work for vacation, sick leave, and family care</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>ESPP (Employee Stock Purchase Plan)</li>\n<li>Retirement plans</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cd352346-abd","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-physical-design-staff-engineer/44408/94169001536","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR/HBM/HBI IP integration","Timing closure","Mixed signal and macro IP integration","Clock tree design"],"x-skills-preferred":["Design Compiler (DC)","IC Compiler II (ICC2)","PrimeTime SI (PT-SI)","Formality (FC)"],"datePosted":"2026-04-24T14:16:07.686Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR/HBM/HBI IP integration, Timing closure, Mixed signal and macro IP integration, Clock tree design, Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), Formality (FC)"}]}