Collaborate with experienced mixed-signal design and verification teams to develop and verify high-speed NRZ and PAM-based SerDes products.

Engage in dynamic PHY IP development, tackling challenging problems and adapting to constant technological advances.

Participate in initial and ongoing training led by top experts, gaining exposure to advanced digital and analog design methodologies.

Contribute to scripting and automation tasks to support design verification processes.

You'll be working on real-world projects, developing high-speed NRZ and PAM-based SerDes products, engaging in dynamic PHY IP development, participating in training sessions, and contributing to scripting and automation tasks.

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You are a skilled and motivated analog design engineer, passionate about developing advanced integrated circuits for high-speed communication systems. With a good understanding of CMOS technologies and track record in designing medium complexity analog circuits, you thrive in fast-paced, collaborative environments. You have expertise in some analog functions such as ADCs, DACs, PLLs, and transceiver blocks, and you are adept at delivering robust designs that meet stringent electrical specifications and reliability constraints. Analytical and detail-oriented, you know how to evaluate the impact of layout parasitics and optimizing for performance, power, and area.

You are comfortable conducting technical reviews, planning design activities, and ensuring that silicon results correlate closely with simulation predictions. Your communication skills enable you to interact effectively within a global and multi-cultural team, and your organizational abilities ensure timely delivery of milestones. You are proactive in problem-solving and continuous improvement, and you value mentorship, sometimes guiding junior engineers. Whether you have industry experience or specialized academic training, you are eager to contribute to cutting-edge projects that power innovations in mobile, automotive, cloud, HPC, AI, IoT, 5G, and storage. Inclusivity, diversity, and collaboration are important to you, and you are ready to make a significant impact at Synopsys.

Design and develop medium complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards. Define and plan analog design activities, setting clear milestones and deliverables for project success. Prepare and conduct technical design reviews, identifying improvements, tracking actions, and ensuring best practices are followed. Evaluate and minimize the impact of layout parasitic effects by collaborating closely with layout teams, optimizing circuit performance, power, and area. Perform silicon correlation with simulation results, analyzing discrepancies and driving design refinements. Engage with a global, multi-cultural, and cross-functional R&D team, contributing to a collaborative and innovative work environment.

Accelerate the development of industry-leading SerDes IP products, supporting diverse markets such as mobile, automotive, cloud computing, HPC, AI, IoT, 5G, and storage, enabling high-speed chip-to-chip communications in next-generation devices. Enhance Synopsys' reputation as a provider of silicon-proven IP by delivering reliable, high-performance analog designs. Reduce risk for customers by ensuring robust correlation between simulation and silicon, leading to differentiated products in the marketplace. Foster innovation and continuous improvement within the analog and mixed-signal R&D team, setting benchmarks for technical excellence.

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You will be comfortable conducting technical reviews, planning design activities, and ensuring that silicon results correlate closely with simulation predictions. Your communication skills will enable you to interact effectively within a global and multi-cultural team, and your organizational abilities will ensure timely delivery of milestones. You will be proactive in problem-solving and continuous improvement, and you will value mentorship, sometimes guiding junior engineers.

You will join Synopsys' fast-growing analog and mixed-signal R&D team, dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. The team is global, dynamic, and cross-functional, working collaboratively to deliver world-class products that power innovations across multiple industries.

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