{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/cxl"},"x-facet":{"type":"skill","slug":"cxl","display":"Cxl","count":7},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_14ac1088-f19"},"title":"ASIC Digital Design, Architect","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. You can define and executing a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.</p>\n<p>What You’ll Be Doing:</p>\n<p>Defining and developing ASIC RTL design and verification at both chip and block levels.\nCreating and executing design plans for complex digital designs, particularly focusing on DDR, PCIe,CXL,UAL, UCIe IO protocols.\nCollaborating with cross-functional teams to ensure seamless integration and functionality of designs.\nUtilizing advanced design and verification methodologies and tools to achieve high-quality results.\nMentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.\nCommunicating with internal and external stakeholders to align on project goals and deliverables.</p>\n<p>The Impact You Will Have:</p>\n<p>Enhancing the reliability and performance of Synopsys’ digital design processes.\nDriving innovations in DDR, PCIe, UAL, UCIe technology, contributing to the development of cutting-edge semiconductor solutions.\nImproving time-to-market for high-performance silicon chips through efficient methodologies.\nBuilding and nurturing a highly skilled development team, elevating overall project quality.\nInfluencing strategic decisions that shape the future of Synopsys’ capabilities.\nEnsuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.</p>\n<p>What You’ll Need:</p>\n<p>Extensive experience in ASIC RTL design.\nIn-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications.\nProficiency in advanced digital design tools and methodologies.\nStrong problem-solving skills and the ability to work independently.\nExcellent communication skills for effective collaboration with diverse teams.</p>\n<p>Who You Are:</p>\n<p>A visionary leader with a strategic mindset.\nA mentor who fosters talent and encourages innovation.\nA proactive problem solver who thrives in complex environments.\nAn effective communicator with the ability to convey technical concepts to a broad audience.\nA team player who values collaboration and diversity.</p>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will join a dynamic and innovative team focused on advancing Synopsys&#39; design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_14ac1088-f19","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/dublin/asic-digital-design-architect/44408/92736415760","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design","DDR","PCIe","CXL","UAL","UCIe","AMBA","advanced digital design tools","methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:24:48.989Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Dublin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design, DDR, PCIe, CXL, UAL, UCIe, AMBA, advanced digital design tools, methodologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ec579fde-89b"},"title":"R&D Engineering, Architect- FPGA Design-PCIe Protocol","description":"<p>You are a visionary engineering leader with deep expertise in FPGA design and advanced protocol integration, ready to architect and deliver solutions that bridge real-world interfaces with cutting-edge emulation and prototyping platforms.</p>\n<p>Designing, developing, and maintaining Speed Adapter solutions for advanced protocols, including PCIe and CXL.\nImplementing protocol functionality on FPGA-based platforms to bridge real-world I/O with DUTs running at reduced speeds on emulation and prototyping systems.\nCollaborating with IP, emulation, and prototyping teams to deliver comprehensive, end-to-end system-level validation solutions.\nDeveloping and debugging RTL, firmware, and system-level components for Speed Adapter products.\nSupporting seamless integration with ZeBu and HAPS platforms, including creating example designs and reference flows.\nParticipating in customer escalations, conducting root-cause analysis, and delivering solutions for complex system-level issues.\nContributing to roadmap planning, feature definition, and technical differentiation versus competitive solutions.</p>\n<p>Enable customers to connect pre-silicon designs to real devices, testers, and hosts with unmatched fidelity and performance.\nAdvance industry-leading system-level validation technology for top semiconductor and hyperscale customers.\nShape the adoption and implementation of next-generation protocols such as PCIe Gen6/Gen7 and CXL3.x/4.0.\nDrive innovation in hardware-assisted verification, influencing patent-pending technologies that differentiate Synopsys solutions.\nEnhance integration across IP, emulation, prototyping, and real-world connectivity to deliver robust validation platforms.\nSupport global teams and customers, fostering technical excellence and collaborative problem-solving.</p>\n<p>12 years+ relevant experience\nBachelor&#39;s or Master&#39;s degree in Electrical Engineering, Computer Engineering, or related field.\nStrong hands-on experience with PCIe and/or CXL protocols, including implementation and debugging.\nSolid understanding of digital design, RTL development, and FPGA-based systems.\nExperience with system-level validation, emulation, or prototyping environments.\nFamiliarity with high-speed serial interfaces and real-world I/O connectivity.\nStrong debugging skills across RTL, firmware, and hardware/software boundaries.\nAbility to work effectively in a cross-geography, cross-functional team.</p>\n<p>Innovative thinker with a strategic mindset.\nCollaborative team player who values diverse perspectives.\nExcellent communicator and technical mentor.\nResilient problem-solver, able to navigate ambiguity and complexity.\nCustomer-focused, with a commitment to delivering high-impact solutions.\nAdaptable and proactive, eager to stay ahead in a fast-evolving technology landscape.</p>\n<p>You&#39;ll join the Speed Adapter engineering team within Synopsys&#39; HW-Assisted Verification (HAV) organization.\nThis talented group is dedicated to developing and deploying industry-leading Speed Adapter solutions that bridge advanced protocols and real-world interfaces with ZeBu emulation and HAPS prototyping platforms.\nThe team collaborates globally across IP, emulation, and prototyping domains to deliver robust, high-performance system validation solutions, directly impacting the success of top semiconductor and hyperscale customers.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.\nOur total rewards include both monetary and non-monetary offerings.\nYour recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.\nSynopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses.\nSynopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.\nThe actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education.\nYour recruiter can share more specific details on the total rewards package upon request.</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world.\nWe feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.\nWe&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ec579fde-89b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/r-and-d-engineering-architect-fpga-design-pcie-protocol/44408/92655118112","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$208,000 - $312,000","x-skills-required":["FPGA design","Advanced protocol integration","PCIe and CXL protocols","Digital design","RTL development","System-level validation","Emulation and prototyping environments","High-speed serial interfaces","Real-world I/O connectivity","Debugging skills"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:28.918Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"FPGA design, Advanced protocol integration, PCIe and CXL protocols, Digital design, RTL development, System-level validation, Emulation and prototyping environments, High-speed serial interfaces, Real-world I/O connectivity, Debugging skills","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":208000,"maxValue":312000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e0507188-1b6"},"title":"ASIC Digital Design, Architect","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as HBM, DDR, PCIe/CXL, AMBA and its applications. You can define and execute a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Defining and developing ASIC RTL design and verification at both chip and block levels.</li>\n<li>Creating and executing design plans for complex digital designs, particularly focusing on HBM, PCIe/CXL and AMBA protocols.</li>\n<li>Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.</li>\n<li>Utilizing advanced design and verification methodologies and tools to achieve high-quality results.</li>\n<li>Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.</li>\n<li>Communicating with internal and external stakeholders to align on project goals and deliverables.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Enhancing the reliability and performance of Synopsys’ digital design processes.</li>\n<li>Driving innovations in HBM, PCIe/CXL and AMBA technology, contributing to the development of cutting-edge semiconductor solutions.</li>\n<li>Improving time-to-market for high-performance silicon chips through efficient methodologies.</li>\n<li>Building and nurturing a highly skilled development team, elevating overall project quality.</li>\n<li>Influencing strategic decisions that shape the future of Synopsys’ capabilities.</li>\n<li>Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Extensive experience in ASIC RTL design.</li>\n<li>In-depth knowledge of HBM, PCIe, CXL, AMBA and similar IO protocols and their applications.</li>\n<li>Proficiency in advanced digital design tools and methodologies.</li>\n<li>Strong problem-solving skills and the ability to work independently.</li>\n<li>Excellent communication skills for effective collaboration with diverse teams.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>A visionary leader with a strategic mindset.</li>\n<li>A mentor who fosters talent and encourages innovation.</li>\n<li>A proactive problem solver who thrives in complex environments.</li>\n<li>An effective communicator with the ability to convey technical concepts to a broad audience.</li>\n<li>A team player who values collaboration and diversity.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will join a dynamic and innovative team focused on advancing Synopsys&#39; design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e0507188-1b6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/dublin/asic-digital-design-architect/44408/91458064944","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design","HBM","DDR","PCIe/CXL","AMBA","advanced digital design tools","methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:54.282Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Dublin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design, HBM, DDR, PCIe/CXL, AMBA, advanced digital design tools, methodologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b4d3cb52-7c4"},"title":"Senior ASIC Verification Engineer, Coherent High Speed Interconnect","description":"<p>We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect team. For two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of modern visual computing - the field has grown to encompass video games, movie production, product design, medical diagnosis, and scientific research.</p>\n<p>Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from meaningful amounts of data - has shown to be deeply effective at solving the most sophisticated problems in everyday life.</p>\n<p>As a Senior ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high speed coherent interconnects for our mobile SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li>In this position, you will be responsible for verification of high-speed coherent interconnect design, architecture and golden models.</li>\n<li>You will be responsible for micro-architecture using sophisticated verification methodologies.</li>\n<li>As a member of our verification team, you&#39;ll understand the design &amp; implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design. This role will collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Bachelors or Master’s Degree (or equivalent experience)</li>\n<li>3+ years of relevant verification experience</li>\n<li>Experience in architecting test bench environments for unit level verification</li>\n<li>Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies</li>\n<li>Prior Design or Verification experience of Coherent high-speed interconnects</li>\n<li>Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful</li>\n<li>Strong background developing TB&#39;s from scratch using SV and UVM methodology is desired</li>\n<li>C++ programming language experience, scripting ability and an expertise in System Verilog</li>\n<li>Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)</li>\n<li>Strong debugging and analytical skills</li>\n<li>Experienced communication and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.</li>\n</ul>\n<p>NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you&#39;re creative and autonomous, we want to hear from you.</p>\n<p>You will also be eligible for equity and benefits.</p>\n<p>Applications for this job will be accepted at least until March 13, 2026.</p>\n<p>This posting is for an existing vacancy.</p>\n<p>NVIDIA uses AI tools in its recruiting processes.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b4d3cb52-7c4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://nvidia.wd5.myworkdayjobs.com","logo":"https://logos.yubhub.co/nvidia.com.png"},"x-apply-url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Verification-Engineer--Coherent-High-Speed-Interconnect_JR2010025","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verification of high-speed coherent interconnect design, architecture and golden models","Micro-architecture using sophisticated verification methodologies","Testbenches, BFMs, Checkers, Monitors","System Verilog","C++ programming language","Design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)"],"x-skills-preferred":["Random stimulus along with functional coverage and assertion-based verification methodologies","Prior Design or Verification experience of Coherent high-speed interconnects","Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI"],"datePosted":"2026-03-09T20:46:52.056Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"US, CA, Santa ClaraUS, MA, WestfordUS, TX, AustinUS, OR, Hillsboro"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verification of high-speed coherent interconnect design, architecture and golden models, Micro-architecture using sophisticated verification methodologies, Testbenches, BFMs, Checkers, Monitors, System Verilog, C++ programming language, Design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), Random stimulus along with functional coverage and assertion-based verification methodologies, Prior Design or Verification experience of Coherent high-speed interconnects, Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_48da4c00-386"},"title":"Design Architect (PCIe/CXL Expert)","description":"<p>You are a visionary and highly experienced logic design expert with a passion for building next-generation hardware solutions. With a strong foundation in PCI Express (PCIe) and/or Compute Express Link (CXL) protocols, you thrive in challenging technical environments, pushing the boundaries of what’s possible in high-speed, complex SoC-class platforms. Your background combines deep hands-on expertise in FPGA architecture, RTL design, and hardware validation, making you a go-to leader for mission-critical projects. You excel at architecting robust, production-quality subsystems and are adept at navigating the intricacies of hardware/software co-design and debugging.</p>\n<p>You are a natural collaborator and mentor, able to bridge the gap between technical and non-technical stakeholders. Your global perspective and excellent communication skills enable you to work seamlessly with cross-functional teams and customers around the world. You are energized by opportunities to lead, whether it’s guiding feature rollouts, solving tough engineering challenges, or supporting cutting-edge customer deployments. Always eager to learn and adapt, you stay at the forefront of industry advances in FPGA, high-speed protocols, and system design. Your commitment to quality, innovation, and continuous improvement sets you apart as a leader in your field.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Architecting, designing, and implementing PCIe/CXL-based FPGA subsystems for advanced SoC emulation and prototyping platforms.</li>\n<li>Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs, ensuring high performance and efficient resource usage.</li>\n<li>Designing and integrating high-speed serial interfaces, DMA engines, memory/cache-coherent protocols, and complex system interconnects.</li>\n<li>Leading hardware validation and debugging activities across both hardware and software domains to deliver robust, production-quality solutions.</li>\n<li>Collaborating with R&amp;D, Applications, Field Engineering, and Marketing teams to gather requirements, define features, and support global customer deployments.</li>\n<li>Driving alpha/beta feature rollout, providing expert technical support, and ensuring successful adoption of ZeBu/HAPS platforms by customers worldwide.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enabling industry-leading SoC emulation and prototyping platforms that accelerate time-to-market for Synopsys customers.</li>\n<li>Delivering high-performance, reliable hardware solutions that set benchmarks in PCIe/CXL protocol integration and validation.</li>\n<li>Enhancing the capabilities of ZeBu and HAPS platforms, empowering semiconductor companies to innovate faster and more efficiently.</li>\n<li>Driving adoption of advanced emulation technologies across AI, server, storage, and data center markets.</li>\n<li>Mentoring and guiding engineering teams, fostering a culture of technical excellence and innovation.</li>\n<li>Building lasting partnerships with global customers by providing expert-level support and thought leadership in high-speed protocol design</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.</li>\n<li>12+ years of experience in ASIC/FPGA logic design for complex SoC-level systems.</li>\n<li>Expert-level knowledge of PCIe (Gen4–Gen6) and/or CXL (1.1/2.0/3.0) protocols, including link training, TLP/CXL.io/cache/mem, flow control, and error handling.</li>\n<li>7+ years of hands-on Xilinx FPGA experience, including transceiver/SERDES integration and FPGA prototyping flows.</li>\n<li>Strong proficiency in RTL development (SystemVerilog/Verilog) and comprehensive understanding of the hardware development cycle (simulation, synthesis, timing analysis).</li>\n<li>Solid grasp of FPGA architecture, clocking/reset design, CDC, and debugging high-speed interfaces.</li>\n<li>Experience in Unix/Linux development environments.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative team player with excellent communication skills and a global mindset.</li>\n<li>Proactive problem solver who thrives in dynamic, fast-paced environments.</li>\n<li>Strong technical leader and mentor, passionate about sharing knowledge and guiding teams.</li>\n<li>Detail-oriented, self-motivated, and committed to delivering high-quality, reliable solutions.</li>\n<li>Adaptable and eager to stay updated with the latest industry trends and technologies.</li>\n<li>Customer-focused, with a dedication to supporting and enabling client success.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a world-class, multidisciplinary engineering team passionate about developing state-of-the-art emulation and prototyping solutions. The team values technical excellence, innovation, and collaboration, working closely with global colleagues in R&amp;D, customer support, and product management. Together, you will tackle some of the most complex challenges in hardware design, driving the future of high-speed, scalable SoC platforms for leading-edge industries.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_48da4c00-386","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/shanghai/design-architect-pcie-cxl-expert/44408/92113189568","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["PCIe","CXL","FPGA","RTL design","hardware validation","Unix/Linux development environments","Xilinx FPGA experience","transceiver/SERDES integration","FPGA prototyping flows","SystemVerilog/Verilog","hardware development cycle","simulation","synthesis","timing analysis"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:02:24.768Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Shanghai"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"PCIe, CXL, FPGA, RTL design, hardware validation, Unix/Linux development environments, Xilinx FPGA experience, transceiver/SERDES integration, FPGA prototyping flows, SystemVerilog/Verilog, hardware development cycle, simulation, synthesis, timing analysis"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_98785e57-1a3"},"title":"Principal ASIC Verification Engineer","description":"<p>As a Principal ASIC Verification Engineer at Synopsys, you will be responsible for partnering with design teams to define verification requirements, developing test plans from specifications, and building and maintaining UVM testbenches and agents.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Partnering with design teams to define verification requirements</li>\n<li>Developing test plans from specifications</li>\n<li>Building and maintaining UVM testbenches and agents</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>B.Sc./M.Sc. in a relevant engineering field</li>\n<li>10+ years in ASIC/UVM verification</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_98785e57-1a3","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/munich/principal-asic-verification-engineer/44408/91377529600","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["SystemVerilog","C","Python","TCL/Perl","UVM","SVA","Formal verification"],"x-skills-preferred":["Interface IPs (PCIe, CXL)","AI tools"],"datePosted":"2026-03-06T07:23:17.310Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Munich"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"SystemVerilog, C, Python, TCL/Perl, UVM, SVA, Formal verification, Interface IPs (PCIe, CXL), AI tools"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a1a2c773-6af"},"title":"High Speed Serdes PHY Application Engineer","description":"<p>Opening. Our team is looking for a High Speed Serdes PHY Application Engineer to join the team. This role involves whole SOC design flow from architecture, high speed Interface IP(IIP) integration, synthesis, design for test(DFT), low power design(UPF), CDC/RDC check, static timing analysis(STA), silicon test plan, silicon bring-up and mass production silicon debug.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Work close with customers to understand new requests or customization feature from customer’s PRD/MRD</li>\n<li>Provide integration training to customers and conduct reviews on their major SoC milestones</li>\n<li>Provide feedback to Synopsys R&amp;D for customization feature or continuous IIP product improvements</li>\n<li>Participate in IIP design reviews to align development with future customer needs</li>\n<li>Creativity and Innovation is highly inspired: such as developing small tools to simplify daily jobs or improving efficiency; authoring application notes for gate-level simulation, silicon debug and physical implementation.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor’s and/or master’s degree in electrical and/or Electronic Engineering, Computer Engineering or Computer Science</li>\n<li>Minimum 5 years of Analog or Mixed signal IP or ASIC Design/Verification/Applications experience is required</li>\n<li>Hands-on experience on circuit design, RTL coding, simulation, synthesis, static timing check, equivalence check, etc.</li>\n<li>Domain knowledge PCI Express, CXL, Ethernet protocols</li>\n<li>Creative results are oriented with the ability to manage multiple tasks concurrently.</li>\n<li>Good verbal and written communication skills in English and ability to interact with customer</li>\n<li>High degree of self-motivation and personal responsibility</li>\n<li>Good inference, reasoning and problem-solving skills, and attention to details</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a1a2c773-6af","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/shenzhen/china-high-speed-serdes-phy-application-engineer/44408/91152874992","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Bachelor’s and/or master’s degree in electrical and/or Electronic Engineering, Computer Engineering or Computer Science","Minimum 5 years of Analog or Mixed signal IP or ASIC Design/Verification/Applications experience","Hands-on experience on circuit design, RTL coding, simulation, synthesis, static timing check, equivalence check, etc.","Domain knowledge PCI Express, CXL, Ethernet protocols","Creative results are oriented with the ability to manage multiple tasks concurrently.","Good verbal and written communication skills in English and ability to interact with customer","High degree of self-motivation and personal responsibility","Good inference, reasoning and problem-solving skills, and attention to details"],"x-skills-preferred":["Scripting languages (Tcl, Perl, Python, Excel VBA, etc.)","Silicon debug and FPGA/hardware troubleshooting skills","Package, PCB design, SI/PI knowledge will be a plus"],"datePosted":"2026-02-04T16:09:55.932Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Shenzhen"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Bachelor’s and/or master’s degree in electrical and/or Electronic Engineering, Computer Engineering or Computer Science, Minimum 5 years of Analog or Mixed signal IP or ASIC Design/Verification/Applications experience, Hands-on experience on circuit design, RTL coding, simulation, synthesis, static timing check, equivalence check, etc., Domain knowledge PCI Express, CXL, Ethernet protocols, Creative results are oriented with the ability to manage multiple tasks concurrently., Good verbal and written communication skills in English and ability to interact with customer, High degree of self-motivation and personal responsibility, Good inference, reasoning and problem-solving skills, and attention to details, Scripting languages (Tcl, Perl, Python, Excel VBA, etc.), Silicon debug and FPGA/hardware troubleshooting skills, Package, PCB design, SI/PI knowledge will be a plus"}]}