Defining and deploying advanced layout methodologies that accelerate execution, enhance quality, and promote standardized best practices across global teams.

Gathering customer requirements, translating them into clear technical specifications, and ensuring these specifications drive methodology and workflow development.

Developing end-to-end workflows that enhance quality, consistency, and efficiency across Synopsys IP development.

Collaborating closely with cross-functional teams—including Circuit Design, Physical Design, CAD, Product Engineering, and Quality—to enable adoption of methodologies for advanced technology nodes.

Providing technical leadership across distributed teams, aligning planning and execution to meet project goals.

Defining, tracking, and analyzing performance metrics to drive continuous improvement and influence future methodology strategy.

Creating and maintaining comprehensive documentation to ensure clarity, scalability, and long-term usability.

Engaging with internal partners and external customers as a trusted technical representative of the Methodology Team.

Leading innovation in analog/mixed-signal layout flows, combining industry-standard tools and internal automation to validate and evolve methodologies.

Mentoring and supporting junior engineers, enabling skill growth and knowledge sharing across the organization.

Accelerating and improving the reliability of analog/mixed-signal IP development at advanced nodes.

Driving alignment and quality across global design teams through standardized workflows and strong technical leadership.

Strengthening collaboration and knowledge transfer across engineering disciplines.

Influencing organizational and product strategy through methodology innovation and customer insights.

Increasing transparency and maintainability of workflows through high-quality documentation.

Contributing to reinforcing Synopsys’ position as a leader in semiconductor design technology.

5+ years in analog/mixed-signal layout or ASIC physical design, with experience in FinFET and advanced nodes strongly preferred.

Deep knowledge of analog and mixed-signal CMOS layout, device-level considerations, and chip-level integration.

Strong expertise with industry tools such as Synopsys Custom Compiler, Cadence Virtuoso, ICV, Calibre, and related verification flows.

Proven ability to gather customer requirements and convert them into technical specifications.

Demonstrated experience building workflows that improve IP quality, efficiency, and consistency.

Strong organizational skills, attention to detail, and ability to manage multiple complex initiatives simultaneously.

Excellent communication, leadership, and mentoring abilities.

Innovative and proactive in solving complex engineering challenges.

Collaborative, with a talent for working across interdisciplinary teams.

Strategic thinker who balances technical depth with big-picture vision.

Effective communicator, able to convey technical concepts to diverse audiences.

Mentor and coach, dedicated to supporting the growth of others.

Adaptable and resilient in fast-paced and evolving environments.

You will join the Mixed Signal IP Technology and Methodology Team—an advanced physical design group focused on developing full-custom analog and ASIC layout solutions for high-speed integrated circuits. The team is known for its collaborative culture, cutting-edge tool ecosystem, and strong commitment to innovation. As a Staff Engineer, you’ll work closely with experienced layout engineers, CAD specialists, and circuit designers to help define best-in-class methodologies and deliver high-quality solutions for Synopsys’ global customers.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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What you'll do

• Designing and integrating memory leafcells and standard cell layouts.
• Optimizing layouts for speed, area, and power.
• Running and debugging DRC, LVS, and ERC checks.
• Collaborating with circuit and verification engineers.

What you need

• 2+ years in custom, standard cell, or memory layout design.
• Experience with FinFET, DRC, LVS, ERC, and boundary conditions.
• Proficiency in Custom Compiler, ICV, and scripting (Perl, Shell, TCL).

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What you'll do

• Lead the physical layout design of advanced memory IP (SRAM, ROM, eDRAM, etc.) at cell, array, and peripheral levels
• Ensure compliance with foundry process design rules (DRC/LVS) and memory-specific constraints

What you need

• Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or related fields
• Minimum of 5 years of experience in layout design

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