At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, powering self-driving cars, cloud infrastructure, and learning machines.

You Are:

A Staff-level analog/MS engineer who owns complex designs end-to-end, influences architecture, and mentors others. You balance performance, reliability, and schedule in advanced CMOS and communicate clearly across teams.

If you are excited by the prospect of shaping high-speed connectivity in AI, cloud, automotive, and beyond - and you seek to empower some of the world's most advanced systems - this role is your opportunity to make a meaningful impact.

What You'll Be Doing:

• Taking end-to-end ownership of critical analog and mixed-signal blocks in high-speed SERDES designs
• Making architectural and circuit-level tradeoffs to optimize power, performance, area, and reliability
• Defining, verifying, and documenting testbenches for rigorous pre-silicon validation
• Leading custom analog layout coordination, ensuring parasitic awareness and post-layout optimization
• Driving robustness and quality sign-off processes, including PVT, mismatch, aging, reliability, and yield analysis
• Aligning system-level interfaces and usability considerations for seamless integration
• Executing silicon bring-up, characterization, and correlation against design specifications
• Providing technical leadership, mentorship, and guidance within a collaborative, multidisciplinary team

What You'll Need:

• MS/PhD in Electronics/Computer Engineer or equivalent; typically 7+ years or equivalent Staff-level impact
• Deep analog/MS in deep sub-micron CMOS; signal integrity/noise/jitter
• Proven architecture tradeoffs and production silicon experience
• Strong custom analog layout collaboration; post-layout optimization
• Excellent communication; ability to influence across teams

The Team You'll Be A Part Of:

You will join the IP and System Solutions Group, a cornerstone of Synopsys' mission to enable the industry's most advanced silicon. The SERDES team is renowned for developing high-speed interface IP, deployed across a wide range of applications and technology nodes. This multidisciplinary group collaborates closely to deliver high-performance, power-efficient chips, optimizing power, performance, and area (PPA) while accelerating time-to-market. You'll work alongside experts in architecture, circuit design, layout, and system integration, fostering innovation and excellence in every project.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Sr Staff Engineer in Custom Analog Enablement and Methodology, you will propose and develop advanced layout design techniques and methodologies, including specification, prototyping, and building solutions with scripting languages (Tcl/Perl/Python). You will run verification on existing designs to assess PDK update impacts and create innovative scripts to minimize rework. You will collaborate with multiple organizations and teams across global time zones to ensure the design environment is optimized for IP design teams.

Key responsibilities include:

• Proposing and developing advanced layout design techniques and methodologies
• Running verification on existing designs to assess PDK update impacts
• Creating innovative scripts to minimize rework
• Collaborating with multiple organizations and teams across global time zones

The ideal candidate will have a deep understanding of custom analog layout design, especially with sub-5nm FinFet/Gate-All-Around nodes. You will be proficient in scripting languages: Tcl, Perl, and Python for workflow automation and prototyping. You will also have the ability to debug LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports effectively.

This role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Collaborating with local and international teams to develop layouts for complex analog and mixed-signal designs in advanced technology nodes (3nm, 2nm, and beyond).

Utilizing Synopsys suite of tools and full custom analog layout design tools (e.g., Custom Compiler) to create and optimize circuit layouts.

Implementing and verifying designs using industry-leading verification tools such as ICV, Calibre and Star-RCXT...

Developing SERDES sub-circuit layouts (RX, TX, PLL, etc.) and optimizing for signal integrity, including clock/data routes, differential routing, and shielding.

Applying scripting techniques (TCL, Python, etc.) to automate layout processes and improve workflow efficiency.

Ensuring designs meet ESD constraints, mitigate latch-up risks, and optimize for reliability issues such as EM and IR drop.

Designing custom digital logic cell layouts and associated logic path routing for mixed-signal integration.

Refining layouts to minimize parasitic effects and enhance matching, reliability, and performance.

Delivering high-quality IP that powers next-generation semiconductor products for global customers.

Enabling Synopsys to maintain leadership in advanced technology node design and IP development.

Contributing to the creation of reliable, high-performance silicon chips used in communications.

Driving innovation in analog and mixed-signal layout methodologies and tools.

Enhancing cross-team collaboration and knowledge sharing to accelerate project timelines and improve outcomes.

Ensuring robust design practices that minimize risk and maximize reliability, meeting stringent industry standards.

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What you'll do

• Designing and implementing custom analog layout for high-speed SERDES blocks, including TX, RX, and PLLs, in advanced technology nodes.
• Developing floor plans, optimizing power distribution networks, and executing signal routing strategies with a focus on EMIR, parasitic minimization, and yield improvement.

What you need

• 5+ years of hands-on experience in custom analog layout, with a focus on High-Speed SERDES (TX/RX/PLL) in deep submicron technologies.
• Proficiency in floor planning, power grid design, signal routing, and parasitic optimization.
• Expertise in industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor Calibre, Synopsys IC Compiler).
• Strong understanding of EMIR, DRC, LVS, ERC, ANT, ESD, DFM, and PERC verification methodologies.

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