<?xml version="1.0" encoding="UTF-8"?>
<source>
  <jobs>
    <job>
      <externalid>c2bf9f43-9e8</externalid>
      <Title>Pre-Silicon Signoff Lead</Title>
      <Description><![CDATA[<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>
<p>This role is for a Pre-Silicon Signoff Lead who will be responsible for leading simulation and sign-off activities that guarantee reliability and performance. The ideal candidate will have a rich background in high-speed serial communication and advanced transceiver design, with expertise in theoretical modeling and hands-on lab work.</p>
<p>Key responsibilities include collaborating closely with analog, digital, and hardware teams to ensure comprehensive design and verification coverage, developing and maintaining robust simulation and verification plans for IP, and reviewing progress against verification plans through regular meetings with multiple verification teams.</p>
<p>The successful candidate will have a strong command of simulation, verification, and hardware validation processes, with experience in high-speed protocols such as PCIe and Ethernet. They will also have a proven track record of leadership in testbench architecture, planning, cross-site collaboration, and mentoring.</p>
<p>As a member of our world-class engineering team, you will drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications.</p>
<p>If you are an innovative and forward-thinking engineer with a passion for advancing connectivity technologies, we encourage you to apply for this exciting opportunity.</p>
<p style="margin-top:24px;font-size:13px;color:#666;">XML job scraping automation by <a href="https://yubhub.co">YubHub</a></p>]]></Description>
      <Jobtype>full-time</Jobtype>
      <Experiencelevel>senior</Experiencelevel>
      <Workarrangement>onsite</Workarrangement>
      <Salaryrange></Salaryrange>
      <Skills>SystemVerilog, object-oriented verification, UVM/VMM/OVM, assertion-based verification, coverage closure, Python, TCL, Perl, C/C++, high-speed analog and digital design principles, verification flows: analog, cosimulation, digital verification, GLS, formal methods, and emulation</Skills>
      <Category>Engineering</Category>
      <Industry>Technology</Industry>
      <Employername>Synopsys</Employername>
      <Employerlogo>https://logos.yubhub.co/careers.synopsys.com.png</Employerlogo>
      <Employerdescription>Synopsys is a leading provider of electronic design automation (EDA) software and services. Its technology is used to design and verify semiconductor products.</Employerdescription>
      <Employerwebsite>https://careers.synopsys.com</Employerwebsite>
      <Compensationcurrency></Compensationcurrency>
      <Compensationmin></Compensationmin>
      <Compensationmax></Compensationmax>
      <Applyto>https://careers.synopsys.com/job/mississauga/pre-silicon-signoff-lead-16513/44408/93247557808</Applyto>
      <Location>Mississauga</Location>
      <Country></Country>
      <Postedate>2026-04-05</Postedate>
    </job>
    <job>
      <externalid>e7c94150-83c</externalid>
      <Title>R&amp;D Engineering, Principal Engineer- 15024</Title>
      <Description><![CDATA[<p>Opening.</p>
<p><strong>What you&#39;ll do</strong></p>
<p>Collaborating closely with analog, digital, and hardware teams to ensure holistic design and verification coverage.</p>
<ul>
<li>Developing and maintaining comprehensive simulation and verification plans for IP, aligning with reliability and performance targets.</li>
</ul>
<p><strong>What you need</strong></p>
<ul>
<li>MSc or PhD in Electrical/Computer Engineering, with 10+ years of relevant industry experience.</li>
</ul>
<p><strong>Why this matters</strong></p>
<p>Advance high-speed connectivity for enterprise and hyperscale applications worldwide.</p>
<p style="margin-top:24px;font-size:13px;color:#666;">XML job scraping automation by <a href="https://yubhub.co">YubHub</a></p>]]></Description>
      <Jobtype>full-time</Jobtype>
      <Experiencelevel>senior</Experiencelevel>
      <Workarrangement>onsite</Workarrangement>
      <Salaryrange></Salaryrange>
      <Skills>MSc or PhD in Electrical/Computer Engineering, 10+ years of relevant industry experience, High-speed protocols—PCIe and Ethernet, SystemVerilog, object-oriented verification, UVM/VMM/OVM, and assertion-based verification, coverage closure expertise, Strong scripting/programming: Python, TCL, Perl, C/C++, In-depth knowledge of high-speed analog and digital design principles, Familiarity with verification flows: analog, co-simulation, digital verification, GLS, formal methods, and emulation, Proven leadership: testbench architecture, planning, cross-site collaboration, and mentoring, Signal processing, Hardware validation</Skills>
      <Category>Engineering</Category>
      <Industry>Technology</Industry>
      <Employername>Synopsys</Employername>
      <Employerlogo>https://logos.yubhub.co/careers.synopsys.com.png</Employerlogo>
      <Employerdescription>Synopsys is a leading provider of electronic design automation (EDA) software and IP solutions. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</Employerdescription>
      <Employerwebsite>https://careers.synopsys.com</Employerwebsite>
      <Compensationcurrency></Compensationcurrency>
      <Compensationmin></Compensationmin>
      <Compensationmax></Compensationmax>
      <Applyto>https://careers.synopsys.com/job/mississauga/r-and-d-engineering-principal-engineer-15024/44408/91213465776</Applyto>
      <Location>Mississauga</Location>
      <Country></Country>
      <Postedate>2026-02-04</Postedate>
    </job>
  </jobs>
</source>