Key responsibilities include:

• Developing high-quality C/C++ code tailored specifically for V-Bat aircraft, ensuring optimal performance, reliability, and safety.
• Participating in architecture, design, and code reviews
• Leading cross-functional teams to create systems of software features to implement advanced robotic avionics capabilities
• Integrating software from multiple departments to include firmware, software test and verification, Autonomy AI, and Ground Control Stations (GCS)
• Developing software systems to implement and integrate interfaces to modern avionics sensors, sub-systems, and payloads
• Facilitating the design process for updates to the software system architecture
• Using modern software development tools and processes to capture our existing architecture and design future architectures
• Collaborating to define and extend systems engineering processes
• Reporting status, risks, accomplishments, expectations to senior leadership
• Working with the V-Bat production teams to manufacture UAVs in-house.

Requirements include:

• Demonstrated track record of assuming ownership over development processes and features and delivering outstanding outcomes
• Proven track record of successfully shipping products, showcasing the ability to navigate through development cycles, overcome obstacles, and deliver high-quality solutions to meet project deadlines and exceed client expectations in a fast-paced environment
• Proactively identifying opportunities for improvement within software development projects, demonstrating initiative to propose and implement innovative solutions that enhance efficiency, quality, and overall project success and V-Bat reliability
• B.S., M.S, PhD degree in Systems Engineering, Software Engineering, Computer Science or STEM (Science, Technology, Engineering, or Mathematics) discipline, such as Aerospace, Mechanical, or Electrical Engineering
• Strong embedded software development experience in C/C+
• Strong knowledge of embedded software, kernel development, BSPs or other systems software components
• Good understanding of computer architecture, operating systems, and network protocols fundamentals
• Experience producing high-quality technical documentation, including architecture, detailed designs, and test plans

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Our team is focused on making boats go and perform tasks with no human involvement. This job is available at multiple levels, including entry, senior, and staff.

The successful candidate will develop algorithms and models which allow boats to sense and navigate, as well as develop metrics which allow quantitative analysis of improvements and regressions in boat performance.

Responsibilities:

• Develop algorithms and models which allow boats to sense and navigate
• Develop metrics which allow quantitative analysis of improvements and regressions in boat performance
• Analyze and work with large data systems to enable model training and evaluation

Requirements:

• Strong programming fundamentals
• Extensive programming experience and demonstrated ability to work on large systems
• Computing Fundamentals
• A general understanding of operating systems and or similar large scale systems
• An understanding of basic computer architecture
• A demonstrated willingness to learn and pivot based on new information

Useful Skills:

• Familiarity with deep learning frameworks (e.g., TensorFlow, PyTorch)
• Understanding of various filters and their applications
• Proficiency in Rust
• Experience with maritime or autonomous vehicle projects
• Experience with signals processing or sensor fusion
• Experience with low latency inference and tracking pipelines
• Experience with path planning algorithms
• Experience training and deploying multi modal models
• Experience with various sensors including radar, cameras, and lidar
• Experience developing and optimizing deployed ML systems

Physical Demands:

• Prolonged periods of sitting at a desk and working on a computer
• Occasional standing and walking within the office
• Manual dexterity to operate a computer keyboard, mouse, and other office equipment
• Visual acuity to read screens, documents, and reports
• Occasional reaching, bending, or stooping to access file drawers, cabinets, or office supplies
• Lifting and carrying items up to 20 pounds occasionally (e.g., office supplies, packages)

Benefits:

• Medical Insurance: Comprehensive health insurance plans covering a range of services
• Dental and Vision Insurance: Coverage for routine dental check-ups, orthodontics, and vision care
• Saronic pays 100% of the premium for employees and 80% for dependents
• Time Off: Generous PTO and Holidays
• Parental Leave: Paid maternity and paternity leave to support new parents
• Competitive Salary: Industry-standard salaries with opportunities for performance-based bonuses
• Retirement Plan: 401(k) plan
• Stock Options: Equity options to give employees a stake in the company’s success
• Life and Disability Insurance: Basic life insurance and short- and long-term disability coverage
• Additional Perks: Free lunch benefit and unlimited free drinks and snacks in the office

Additional Information:

This role requires access to export-controlled information or items that require “U.S. Person” status. As defined by U.S. law, individuals who are any one of the following are considered to be a “U.S. Person”: (1) U.S. citizens, (2) legal permanent residents (a.k.a. green card holders), and (3) certain protected classes of asylees and refugees, as defined in 8 U.S.C. 1324b(a)(3).

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At Synopsys, we're seeking a Staff Engineer (Machine Learning) to join our Machine Learning Center of Excellence (ML CoE) within our Silicon Design & Verification business. As a key member of this highly innovative team, you'll be responsible for designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.

Key Responsibilities:

• Designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.
• Integrating ML-driven solutions into a variety of EDA tools, building on the success of DSO.ai and expanding beyond physical implementation.
• Automating chip design flows with scripting languages (Perl, Python, Tcl, shell scripts) to increase efficiency and reproducibility.
• Collaborating with cross-functional teams to identify design bottlenecks and propose innovative solutions for enhancing power, performance, and area (PPA).
• Conducting research and prototyping novel chip design methodologies, demonstrating new concepts, and driving them to productization.
• Staying current with industry trends in silicon design, machine learning, and EDA, and championing their adoption within Synopsys' product lines.

Impact:

• Accelerate the development of next-generation silicon chips by enabling smarter, faster design optimization through AI and machine learning.
• Reduce time-to-market for customers by eliminating months off project schedules, directly impacting their competitiveness.
• Enhance the performance, power efficiency, and cost-effectiveness of chips designed with Synopsys' tools, driving industry-leading outcomes.
• Shape the evolution of EDA software by pioneering ML-driven methodologies adopted by semiconductor leaders worldwide.
• Enable customers to autonomously explore vast design spaces, achieving optimal results with reduced manual intervention.
• Strengthen Synopsys' position as the global leader in silicon design and verification by delivering innovative, high-impact solutions.

Requirements:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline.
• 5+ years of experience in chip design, EDA, or related fields.
• Expertise in at least one domain of chip design (architectural, micro-architectural, RTL, circuit, or physical design).
• Strong programming and automation skills using Perl, Python, Tcl, or shell scripting.
• Solid understanding of Unix/Linux environments and design flow automation.
• Knowledge of industry-standard RTL design, synthesis, place and route, verification, ATPG, custom-circuit design, and signoff flows.
• Familiarity with low power design techniques, computer architecture, and machine learning principles.

Who We're Looking For:

• A creative problem solver who approaches challenges with curiosity and resilience.
• An effective communicator who collaborates well with multidisciplinary teams.
• Detail-oriented with a passion for quality and continuous improvement.
• Self-driven, adaptable, and comfortable with ambiguity in fast-paced environments.
• Committed to learning, growth, and sharing knowledge with others.

The Team You'll Be A Part Of:

You'll join the Machine Learning Center of Excellence (ML CoE) within Synopsys' Silicon Design & Verification business. This highly innovative team is at the forefront of integrating AI and ML into chip design, collaborating with experts across architecture, implementation, and verification. Together, you'll drive the development of ML-based design optimization solutions and set new standards for the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You will work alongside system architects, chip and board designers, software/firmware engineers, HW/SW applications engineers, process/reliability specialists, ATE engineers, and operations in a dynamic and high-energy work environment to bring industry-defining products to market.

Your responsibilities will include:

• Collaborating with cross-functional teams to craft essential next-generation product features that are important for performance, power optimization, and power management.
• Collaborating to craft tools for post-silicon work, build post-silicon methodologies to characterize silicon power, correlate silicon behavior with simulation.
• Working with various Arch & Design teams to come up with test plans of new features.
• Collaborating with other validation & bring-up teams to bring up/characterize silicon power and power saving features.
• Working with design & estimation teams to correlate with pre-silicon expectation, work with HW and SW teams to do the vital tuning and optimization of silicon power.
• Developing power consumption models to be used in binning, productization, and customer application notes, characterize and develop various power control mechanisms together with Arch/Design/SW teams.

We need to see:

• B. Tech or M. Tech in Electronics Engineering stream, with 3+ years related work experience, excellent problem-solving, collaborative, and interpersonal skills.
• Strong understanding of aspects related to silicon power and performance, technology node impacts, Hardware and Software interactions at system level.
• Hands-on experience with silicon bring up, validation, and productization, good knowledge in board and system design considerations, Power supply design.
• Very good problem-solving and hardware debugging skills, very good data analysis and logical reasoning skills.
• Strong familiarity with HW lab environment and understanding of various lab equipment.
• Experience in working with windows. Linux exposure is highly preferred.
• Working experience with scripting languages like perl and/or python is a plus point.
• Must be a great teammate and ready to collaborate with global teams from diverse cultural backgrounds in a high-energy environment.
• Exposure to critical path analysis, power analysis, process technologies, transistor/device physics, silicon reliability, and aging mechanisms.
• Background with power supply and substrate noise analysis and mitigation. Exposure to digital design, circuit analysis, computer architecture, BIOS, drivers, and software applications.

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As a TPU Kernel Engineer, you'll be responsible for identifying and addressing performance issues across many different ML systems, including research, training, and inference. A significant portion of this work will involve designing and optimising kernels for the TPU. You will also provide feedback to researchers about how model changes impact performance.

You may be a good fit if you:

• Have significant experience optimising ML systems for TPUs, GPUs, or other accelerators
• Are results-oriented, with a bias towards flexibility and impact
• Pick up slack, even if it goes outside your job description
• Enjoy pair programming (we love to pair!)
• Want to learn more about machine learning research
• Care about the societal impacts of your work

Strong candidates may also have experience with:

• High performance, large-scale ML systems
• Designing and implementing kernels for TPUs or other ML accelerators
• Understanding accelerators at a deep level, e.g. a background in computer architecture
• ML framework internals
• Language modeling with transformers

Representative projects:

• Implement low-latency, high-throughput sampling for large language models
• Adapt existing models for low-precision inference
• Build quantitative models of system performance
• Design and implement custom collective communication algorithms
• Debug kernel performance at the assembly level

Logistics

• Education requirements: We require at least a Bachelor's degree in a related field or equivalent experience.
• Location-based hybrid policy: Currently, we expect all staff to be in one of our offices at least 25% of the time. However, some roles may require more time in our offices.
• Visa sponsorship: We do sponsor visas! However, we aren't able to successfully sponsor visas for every role and every candidate. But if we make you an offer, we will make every reasonable effort to get you a visa, and we retain an immigration lawyer to help with this.

We encourage you to apply even if you do not believe you meet every single qualification. Not all strong candidates will meet every single qualification as listed. Research shows that people who identify as being from underrepresented groups are more prone to experiencing imposter syndrome and doubting the strength of their candidacy, so we urge you not to exclude yourself prematurely and to submit an application if you're interested in this work.

Your safety matters to us. To protect yourself from potential scams, remember that Anthropic recruiters only contact you from @anthropic.com email addresses. In some cases, we may partner with vetted recruiting agencies who will identify themselves as working on behalf of Anthropic. Be cautious of emails from other domains. Legitimate Anthropic recruiters will never ask for money, fees, or banking information before your first day. If you're ever unsure about a communication, don't click any links—visit anthropic.com/careers directly for confirmed position openings.

How we're different

We believe that the highest-impact AI research will be big science. At Anthropic we work as a single cohesive team on just a few large-scale research efforts. And we value impact — advancing our long-term goals of steerable, trustworthy AI — rather than work on smaller and more specific puzzles. We view AI research as an empirical science, which has as much in common with physics and biology as with traditional efforts in computer science. We're an extremely collaborative group, and we host frequent research discussions to ensure that we are pursuing the highest-impact work at any given time. As such, we greatly value communication skills.

The easiest way to understand our research directions is to read our recent research. This research continues many of the directions our team worked on prior to Anthropic, including: GPT-3, Circuit-Based Interpretability, Multimodal Neurons, Scaling Laws, AI & Compute, Concrete Problems in AI Safety, and Learning from Human Preferences.

Come work with us!

Anthropic is a public benefit corporation headquartered in San Francisco. We offer competitive compensation and benefits, optional equity donation matching, generous vacation and parental leave, flexible working hours, and a lovely office space in which to collaborate with colleagues.

Guidance on Candidates' AI Usage:

Learn about our policy for using AI in our application process

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Design Verification Engineer

Location

San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Scaling

Compensation

• $226K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team:

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.

In this role you will:

• Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.

• Define verification plans based on architecture and microarchitecture specs.

• Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.

• Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.

• Drive bug triage, root cause analysis, and work closely with design teams on resolution.

• Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.

You might thrive in this role if you have:

• BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.

• Proven success verifying complex IP or SoC designs in industry-standard flows

• Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).

• Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.

• Familiarity with performance modeling, formal verification, or emulation is a plus.

• Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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Location

San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Scaling

Compensation

• $342K – $555K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

Benefits

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

As an Engineer on our hardware optimization and co-design team, you will co-design future hardware from different vendors for programmability and performance. You will work with our kernel, compiler and machine learning engineers to understand their unique needs related to ML techniques, algorithms, numerical approximations, programming expressivity, and compiler optimizations. You will evangelize these constraints with various vendors to develop and influence future hardware architectures towards efficient training and inference on our models. If you are excited about efficiently distributing a large language model across devices, dealing with and optimizing system-wide/rack-wide networking bottlenecks and eventually tailoring the compute pipe and memory hierarchy of the hardware platform, simulating workloads at different abstractions and working closely with our partners, this is the perfect opportunity!

In this role, you will:

• Co-design future hardware for programmability and performance with our hardware vendors

• Assist hardware vendors in developing optimal kernels and add support for it in our compiler

• Develop performance estimates for critical kernels for different hardware configurations and drive decisions on compute core and memory hierarchy features

• Build system performance models at different abstraction levels and carry out analysis to drive decisions on scale up, scale out, front end networking

• Work with machine learning engineers, kernel engineers and compiler developers to understand their vision and needs from high performance accelerators

• Manage communication and coordination with internal and external partners

• Influence the roadmap of hardware partners to optimize them for OpenAI’s workloads.

• Evaluate potential partners’ accelerators and platforms.

• As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings.

You might thrive in this role if you have:

• 4+ years of industry experience, including experience harnessing compute at scale and optimizing ML platform code to run efficiently on target hardware.

• Strong experience in software/hardware co-design

• Deep understanding of GPU and/or other AI accelerators

• Experience with CUDA, Triton or a related accelerator programming language

• Experience driving Machine Learning accuracy with low precision formats

• Experience with system performance modeling and analysis to optimize ML model deployment

• Strong coding skills in C/C++ and Python

• Are familiar with the fundamentals of deep learning computing and chip architecture/microarchitecture.

These attributes are nice to have:

• PhD in Computer Science and Engineering with a specialization in Computer Architecture, Parallel Computing. Compilers or other Systems

• Strong understanding of LLMs and challenges related to their training and inference

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Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role you will:

• Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems

• Contribute to architectural studies including performance modeling and feasibility analysis.

• Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.

• Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.

• Build and review performance and functional models to validate design intent.

• Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.

You Might Thrive In This Role If You Have:

• Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.

• Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.

• Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.

• Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.

• Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.

• Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.

• Passion for building industry-leading massive-scale hardware systems.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

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RTL & Codesign Engineer

Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role you will:

• Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems

• Contribute to architectural studies including performance modeling and feasibility analysis.

• Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.

• Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.

• Build and review performance and functional models to validate design intent.

• Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.

You Might Thrive In This Role If You Have:

• Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.

• Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.

• Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.

• Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.

• Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.

• Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.

• Passion for building industry-leading massive-scale hardware systems.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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