In this role, you will manage internal and external stakeholders to bring clarity to our compute technology roadmaps, help prioritise across technical and non-technical teams, and focus on securing and delivering compute capacity.

As a key member of our team, you will work closely with engineering, finance, and partnership teams to drive execution of technical roadmaps, support deal structuring, and manage the operational aspects of our compute partnerships.

This role combines technical program management with elements of strategic operations, partnership development, and financial analysis.

Responsibilities:

• Drive cross-functional coordination across Engineering, Finance, and external partners to define, scope, and deliver on compute partnership initiatives

• Develop and maintain detailed project plans, timelines, and status reporting for technical programs related to compute infrastructure and partnerships

• Partner with engineering leaders to translate technical requirements into actionable roadmaps and track execution against milestones

• Support the structuring and negotiation of strategic compute deals, including financial modelling, term analysis, and vendor evaluation

• Build and maintain relationships with key stakeholders at cloud providers and infrastructure partners

• Develop and manage systems, processes, and documentation to support program management efficiency and stakeholder visibility

• Analyse financial and operational data to inform decision-making on compute capacity planning and vendor strategy

• Provide clear and transparent reporting on program status, issues, and risks to leadership

You might be a good fit if you have:

• 8-10 years of experience in technical product/program management, business development, or strategic partnerships roles at technology companies

• Experience structuring and negotiating strategic customer deals or partnerships within the technology space (cloud services, semiconductors, data centre/infrastructure)

• Background in cloud computing, data centre infrastructure, compute/silicon development, or technology-focused investment banking or consulting

• Familiarity with data centre infrastructure, compute hardware, and/or silicon development cycles

• Comfort with financial analysis and modelling; experience with vendor financing arrangements is a plus

• Strong interpersonal and communication skills with the ability to influence and align diverse stakeholders

• Ability to drive clarity in ambiguous environments and manage competing priorities with high-quality execution

• A track record of managing cross-functional initiatives in fast-paced, scaling technology environments

• A passion for Anthropic's mission and ensuring safe AI development

Strong candidates may also have:

• Experience managing external partnerships with large-scale cloud providers or hardware vendors

• Understanding of AI/ML infrastructure requirements and compute capacity planning

• Experience with vendor financing, equipment leasing, or infrastructure investment analysis

• Background in technical due diligence or technology M&A

The annual compensation range for this role is $250,000-$310,000 USD.

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ASIC Firmware Engineer, Modeling

Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $226K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We are looking for an embedded engineer to help build firmware and associated modeling software for OpenAI’s in house AI accelerator. This role involves designing and developing drivers and functional models for a large array of HW components, writing high throughput and low latency firmware code, investigating bring-up and production issues.

Responsibilities

• Design and implement drivers for hardware peripherals, including those related to AI chips.

• Design and implement functional software models to simulate SoC uncore logic and enable FW testing against the model

• Design and implement low-latency and high throughput embedded SW to manage HW resources.

• Work with adjacent software and hardware teams to implement requirements, debug issues and shape future generations of the hardware.

• Collaborate with vendors to integrate their technologies within our systems.

• Bring up and debug firmware/driver on new platforms.

• Come up with processes and debug issues raised in the field.

• Set up monitoring, integration testing and diagnostics tools.

Qualifications

• 5+ years of experience working in embedded SW space.

• Ability to thrive in ambiguity and learn new technologies.

• Strong programming skills in C/C++ and/or Rust.

• Experience developing high throughput, low latency and multi-threaded code.

• Experience working with real time operating systems (RTOS).

• Experience developing hardware drivers and working with hardware

• Experience with HW/SW co-design

• Knowledge of common embedded protocols, e.g. UART, I2C, SPI, etc.

• Knowledge of microprocessor and common ARM architectures (e.g. AMBA) is a plus.

• Knowledge of PCIe, ethernet and other high BW communication protocols is a plus.

• Experience with GPUs or other compute hardware is a plus.

• Experience deploying large compute clusters is a plus.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

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