Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nAs an ASIC Digital Design Engineer, you will be part of a dynamic and diverse engineering team focused on subsystem and SoC-level verification. The team is committed to technical excellence, innovation, and continuous improvement, working collaboratively to deliver industry-leading solutions for Synopsys' global clients.
\nResponsibilities:
\nDevelop and execute comprehensive verification plans for subsystem features and interfaces. Build, enhance, and maintain UVM-based verification environments for complex RTL designs. Create reusable and scalable testbenches, sequences, checkers, and scoreboards to ensure thorough coverage. Debug simulation failures, analyze waveform-level issues, and drive root-cause analysis to resolution. Collaborate closely with design, architecture, and cross-functional engineering teams to align on specifications and compliance. Define and implement test scenarios, including directed, constrained-random, and corner-case verification. Support regression planning, test execution, and coverage closure activities to ensure quality silicon delivery. Contribute to methodology improvements and best practices in functional verification. Communicate progress, technical findings, and risks effectively with stakeholders and team members.
\nImpact:
\nEnhance the robustness and performance of subsystem and SoC-level designs through rigorous verification processes. Drive the delivery of high-quality silicon solutions that power next-generation technologies. Accelerate time-to-market for Synopsys' clients by ensuring reliable and efficient verification workflows. Improve verification methodologies and contribute to best practices that set industry standards. Foster collaboration across design, architecture, and engineering teams to achieve common goals. Identify and resolve technical risks early, ensuring successful project outcomes and client satisfaction.
\nRequirements:
\nBachelor's or Master's degree in electronics, electrical engineering, or a related field. Minimum 3+ years of hands-on verification experience, preferably in subsystem or SoC-level projects. Strong proficiency in protocols such as PCIe, CXL, UCIe, Ethernet, DDR, or USB. Solid experience with SystemVerilog/UVM and assertion-based verification techniques. Expertise in functional coverage, code coverage, and regression management. Strong debugging skills using simulation and waveform analysis tools. Exposure to formal verification techniques and their application in real-world scenarios.
\nTeam:
\nYou'll join a dynamic and diverse engineering team focused on subsystem and SoC-level verification. The team is committed to technical excellence, innovation, and continuous improvement, working collaboratively to deliver industry-leading solutions for Synopsys' global clients.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
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\nJob Description
\nWe are seeking a Sr Staff Engineer to lead and drive ownership of critical areas of verification alongside a team of talented verification engineers. The successful candidate will define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for Subsystem. They will specify, build, enhance, and maintain state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, integrating RTL, behavioral models. The candidate will also code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.
\nResponsibilities
\nImpact
\nRequirements
\nTeam
\nYou will join the Synopsys Subsystem team, a group of expert engineers at the leading edge of IP integration. The team works in close partnership with all interface IP groups, tools, methodology, and architecture groups across North America, Europe, and Asia. Together, you drive engineering excellence and deliver high-impact Subsystem that powers the world's most advanced silicon solutions.
\nRewards and Benefits
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nAs a Staff Engineer in our ASIC Digital Design team, you will be responsible for leading and driving ownership of critical areas of verification alongside a team of talented verification engineers. You will define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for Subsystem.
\nYour responsibilities will include specifying, building, enhancing, and maintaining state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, integrating RTL and behavioral models. You will also code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.
\nIn addition, you will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met. You will manage regressions and contribute to the continuous improvement of verification strategies and test environments.
\nYou will work closely with RTL designers and architects to ensure functional correctness and collaborate with a global team of experienced verification engineers, fostering knowledge sharing and professional growth.
\nAs a Staff Engineer, you will have the opportunity to make a significant impact on the success of our Subsystem and contribute to the early detection and resolution of critical design issues, reducing time-to-market and silicon re-spins.
\nYou will also enhance Synopsys' reputation as the premier provider of high-speed connectivity IP Subsystem through engineering excellence and innovation, and bolster Synopsys' leadership in chip design by ensuring our IP verification methodologies set industry standards.
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\nThis role is part of the Synopsys Subsystem team, which works in close partnership with all interface IP groups, tools, methodology and architecture groups across North America, Europe, and Asia. Together, you drive engineering excellence and deliver high-impact Subsystem that powers the world’s most advanced silicon solutions.
\nAs a Staff Engineer, you will lead and drive ownership of critical areas of verification alongside a team of talented verification engineers. You will define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for Subsystem.
\nKey responsibilities include:
\nIn this role, you will have the opportunity to work on advanced UCIe/Ethernet/UALink IP integration deployed in the most innovative SoCs. You will collaborate with a global team of experienced verification engineers, fostering knowledge sharing and professional growth.
\nTo succeed in this role, you will need:
\nIf you thrive in a fast-paced, high-impact engineering environment and are driven by a sense of ownership and technical rigor, you will find Synopsys Subsystem organization to be the ideal environment to accelerate your career and make a meaningful impact.
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