You are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR & HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification. You thrive in dynamic environments, bringing a collaborative spirit and a growth mindset to every project. You value diversity and inclusion, recognizing the importance of varied perspectives in driving innovation. With a commitment to accountability, you consistently deliver quality results, demonstrating ownership and initiative in your work. Your communication skills,both verbal and written,enable you to effectively share ideas, provide feedback, and partner with cross-functional teams. You are motivated by the opportunity to work on cutting-edge technologies, always seeking to expand your knowledge and make a meaningful impact. Whether solving complex problems or optimizing layouts for performance, power, and area, you approach challenges with creativity and perseverance. You are ready to join Synopsys in shaping the future of silicon IP, contributing to products that empower customers to succeed in the Era of Smart Everything.

Developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below) Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements. Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles. Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues. Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes. Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.

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You are a dedicated engineer with a passion for analog and mixed-signal IC design, eager to push the boundaries of semiconductor technology. You thrive in environments where innovation, precision, and collaboration are key. Your technical expertise is matched by your curiosity and willingness to continuously learn, adapting to new challenges and technologies. You enjoy working hands-on, taking ownership of the design process from conception to silicon validation. With a keen eye for detail and a strong analytical mindset, you excel at optimizing performance and robustness in high-speed interfaces. You are comfortable navigating complex circuit architectures, and your experience allows you to anticipate issues and implement creative solutions. You value open communication and teamwork, working effectively with layout and lab teams in a multicultural setting. Your documentation skills ensure clarity and reproducibility throughout the design cycle. You are motivated by the opportunity to make a tangible impact on industry-leading products, and you seek growth not only in technical depth but also in architectural responsibility. Ultimately, you are a proactive contributor, ready to help Synopsys shape the next generation of high-speed analog solutions.

Design, analyze, and optimize high-speed analog and mixed-signal circuits such as voltage regulators, DACs, AFE/DFE, TX drivers, serializers, and supporting blocks. Conduct detailed circuit behavior analysis, tuning performance and proposing improvements for power, speed, and robustness. Perform timing closure for small digital blocks using NanoTime, ensuring accurate integration with analog designs. Lead technical interactions with layout teams, guiding floorplanning, matching, and parasitic-aware design to achieve block specifications. Participate actively in design reviews, layout reviews, and silicon bring-up processes to ensure quality and reliability. Support lab characterization and debug, correlating simulation results with silicon measurements for optimal validation. Document architectures, design decisions, testbenches, simulation results, and silicon learnings to maintain clarity and foster knowledge sharing.

Advance Synopsys' leadership in high-speed SerDes IP and analog interface technology. Enable the development of state-of-the-art products used across diverse industries, from data centers to automotive. Drive innovation in design methodologies, influencing future product architectures and performance standards. Enhance cross-functional collaboration, ensuring seamless integration between design, layout, and validation teams. Improve product robustness and yield through meticulous analysis, testing, and documentation. Accelerate time-to-market for cutting-edge chips by optimizing design cycles and validation processes. Contribute to a culture of continuous improvement and technical excellence within Synopsys' engineering community.

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You are a passionate analog design engineer eager to make a tangible impact in pioneering semiconductor technologies. You thrive in fast-paced environments and enjoy collaborating with diverse, talented teams. Your expertise in CMOS circuit design and deep submicron process technologies makes you a valuable contributor to high-performance chip solutions. You are detail-oriented, analytical, and consistently deliver quality results. Your curiosity drives you to explore industry standards such as JEDEC DDR interfaces, and you are comfortable navigating the complexities of ASIC design flows. You communicate clearly and effectively, bridging technical discussions between cross-functional teams. You embrace continuous learning and are always ready to tackle new challenges, leveraging your experience in analog/mixed signal circuitry and ESD concepts. You are motivated by the opportunity to influence the next generation of silicon products and are committed to excellence in every aspect of your work. Your collaborative spirit, adaptability, and drive for innovation make you a perfect fit for Synopsys' world-class engineering community.

Designing DDR I/O circuits for advanced semiconductor products, ensuring alignment with JEDEC interface standards. Implementing CMOS circuit design and layout methodologies to optimize performance and reliability. Collaborating with internal development teams to integrate analog/mixed signal circuitry into ASIC designs. Analyzing and resolving issues related to deep submicron process technologies. Executing assigned circuit design tasks with a focus on product quality and efficiency. Documenting design solutions and communicating technical details clearly to cross-functional stakeholders. Participating in design reviews and contributing to continuous improvement of design flows and practices.

Advance Synopsys' leadership in high-performance DDR interface design for cutting-edge chips. Enhance product reliability and scalability through robust analog design methodologies. Drive innovation in deep submicron process technology applications. Strengthen integration of mixed signal and analog circuitry in ASIC products. Support cross-team collaboration to accelerate product development and delivery. Contribute to Synopsys' reputation for technical excellence and quality in semiconductor solutions.

BTech/MTech in Electrical Engineering or related field (MTech+3 years / BTech+5 years experience). Strong knowledge of CMOS processes and deep submicron process technology issues. Expertise in CMOS circuit design and layout methodology; familiarity with analog/mixed signal circuitry. Understanding of basic ESD concepts (a plus). Experience with ASIC design flow and integration. Knowledge of JEDEC DDR interface requirements, DDR timing, ODT, and SDRAM functionality (preferred).

Analytical thinker with strong problem-solving skills. Effective communicator, both written and verbal, for internal team interactions. Collaborative team player, eager to learn and share knowledge. Detail-oriented and quality-focused in all aspects of design. Adaptable and resilient in dynamic project environments.

You will join a highly skilled Analog/Mixed Signal Design team in Bangalore, focused on delivering innovative DDR I/O circuit solutions for ASIC products. The team values creativity, technical rigor, and collaborative problem-solving, working closely with cross-functional groups to drive product excellence and meet industry standards.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Design circuit for Analog IPs like High Speed IOs, LCDL, Bandgap, High Speed macros for high speed PHY, Clock trees, Calibration circuits...

Analyse and verify to make sure design meet all requirements of functionality, performance, area and reliability.

Work closely with layout engineers to make sure layout quality. Perform post layout verifications.

Perform design characterizations, functionality checks, EMIR analysis, Co-simulations for Logic-Analog full chip operations.

Design analysis  and solve problems of noise, margin, signal integrity, power integrity.

Complete all design quality checks and data quality checks

Do design reviews across global team

Work with digital/system engineer to integrate analog designs into mixed signal system. Perform mixed signal verification which combining both analog and digital blocks.

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In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed (>200Gbps) analog integrated circuits in the latest FinFET process nodes.

Responsibilities:

• Reviewing SerDes standards and architecture documents to develop comprehensive analog sub-block specifications.
• Identifying and refining circuit implementations to achieve optimal power, area, and performance targets.
• Proposing and executing design and verification strategies that leverage advanced simulator features for highest-quality design outcomes.
• Overseeing physical layout to minimize parasitic effects, device stress, and process variation, ensuring robust silicon performance.
• Collaborating closely with digital RTL engineers to develop calibration, adaptation, and control algorithms for analog circuits.
• Presenting simulation data for peer and customer reviews, effectively communicating design decisions and results.
• Mentoring and reviewing the progress of junior engineers, fostering a high-performance team environment.
• Documenting design features, test plans, and methodologies to ensure traceability and reproducibility.
• Consulting on the electrical characterization of analog circuits within the SerDes IP product portfolio.

Impact:

• Drive the development of industry-leading SerDes solutions that enable next-generation high-speed communication interfaces.
• Enhance product competitiveness by delivering robust, low-power, and high-performance analog blocks for global customers.
• Accelerate time-to-market by proposing efficient design and verification strategies that streamline development cycles.
• Champion best practices in layout and design for reliability, contributing to high-yield and manufacturable solutions.
• Advance the technical expertise of the broader team through mentorship and technical leadership.
• Strengthen customer trust by delivering well-documented, silicon-proven solutions and providing expert technical support.
• Contribute to the continuous evolution of Synopsys’ analog and mixed-signal IP portfolio, ensuring ongoing leadership in the semiconductor industry.

Requirements:

• BS/BTech degree and 8+ years of experience in IC design, or MS/MTech/PhD with 6+ years of experience.
• In-depth familiarity with transistor-level circuit design and solid CMOS fundamentals.
• Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.
• Detailed design experience with several of the following: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillators, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
• Expertise in optimizing FinFET CMOS layout to minimize parasitic effects and local device mismatch.
• Awareness of ESD issues and design for reliability, including electromigration, IR-drop, and aging.
• Experience using EDA tools for schematic entry, physical layout, and design verification.
• Strong knowledge of SPICE simulators and simulation methodologies.
• Proficiency in Verilog-A for analog behavioral modeling and simulation control/data capture.
• Programming experience in TCL, Perl, C, Python, or MATLAB.

Team: You will join a high-impact analog/mixed-signal design team renowned for delivering state-of-the-art SerDes IP solutions. The team’s focus is on innovation, quality, and collaboration, working closely with digital design, layout, verification, and product engineering teams.

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We are seeking an expert analog design engineer with a passion for high-speed integrated circuits and a drive to push the boundaries of SERDES technology. As a Sr Staff Engineer, you will lead the design and development of high-performance analog and mixed-signal solutions in advanced process nodes.

Key Responsibilities:

• Reviewing SERDES standards to develop innovative transceiver architectures and sub-block specifications for Multi-Gbps NRZ & PAM4 SERDES IP.
• Investigating and architecting advanced circuit solutions to overcome bottlenecks, achieving breakthroughs in power efficiency, area reduction, and performance.
• Collaborating with cross-functional teams, including analog, digital, and layout engineers,to optimize design and verification strategies for superior quality and project efficiency.
• Presenting and critically reviewing simulation data within project teams and at external industry panels or customer meetings.
• Overseeing physical layout to minimize parasitics, device stress, and process variations, ensuring robust manufacturability and reliability.
• Documenting design features, creating comprehensive test plans, and ensuring traceability throughout the development lifecycle.
• Consulting on electrical characterization of SERDES IP, analyzing customer silicon data, and proposing enhancements or post-silicon updates as needed.

Impact:

• Driving the next generation of high-speed data communication through pioneering SERDES architectures.
• Enabling Synopsys customers to achieve industry-leading performance, power efficiency, and reliability in their products.
• Fostering a culture of technical excellence and innovation within a diverse, high-caliber design team.
• Accelerating project timelines by streamlining design and verification methodologies.
• Enhancing the overall quality and competitiveness of Synopsys IP offerings through expert problem-solving and continuous improvement.
• Mentoring and developing junior engineers, strengthening the team's collective expertise and future leadership pipeline.

Requirements:

• Ph.D. with 6+ years, or M.Sc. with 8+ years of practical analog IC design experience, preferably in Electrical Engineering, Computer Engineering, or a related field.
• Deep expertise in transistor-level circuit design and sound CMOS fundamentals.
• Hands-on design experience with one or more SERDES sub-circuits (e.g., receive equalizers, samplers, drivers, serializers/deserializers, voltage-controlled oscillators, PLLs, bandgap references, ADCs, DACs).
• Proficiency with schematic entry, physical layout, and design verification tools; familiarity with SPICE simulators and simulation methodologies.
• Experience with analog/digital co-design for performance optimization, including calibration, adaptation, and timing handoff.
• Knowledge of reliability and layout effects (EM, IR, aging, matching, proximity, ESD, etc.).
• Proficiency in Verilog-A for analog behavioral modeling, and experience with scripting languages such as TCL, Perl, C, Python, or MATLAB.
• Excellent communication, presentation, and documentation skills.

Team:

• You will join a dynamic, growing analog and mixed-signal design team focused on developing cutting-edge Multi-Gbps SERDES IP.
• The team is composed of passionate engineers from diverse backgrounds, collaborating closely with digital designers, layout specialists, and software/CAD experts.
• Our culture emphasizes technical excellence, innovation, and continuous learning.
• With access to best-in-class design tools and in-house support, this team thrives on solving industry-defining challenges and delivering world-class IP to Synopsys' global customers.

Rewards and Benefits:

• We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
• Our total rewards include both monetary and non-monetary offerings.
• Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Your primary focus will be on collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. You will also be responsible for automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

In addition, you will troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. You will interface directly with customers and Field Application Engineers (FAEs) to gather requirements, provide technical support, and ensure successful deployment of PV solutions.

As a natural collaborator and mentor, you will guide junior team members and foster a supportive team environment. Your excellent communication skills will enable you to engage confidently with customers and FAEs, translating complex requirements into innovative solutions.

Key Responsibilities:

• Develop and validate DRC, LVS, and Fill runsets for the Synopsys IC Validator tool
• Collaborate with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes
• Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python
• Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges
• Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions
• Mentor junior team members and foster a supportive team environment

Requirements:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field
• 5-8 years of hands-on experience in the Physical Verification (PV) domain
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks
• Exposure to competitive EDA tools and awareness of their strengths and limitations

Ideal Candidate:

• Analytical thinker with strong problem-solving abilities and meticulous attention to detail
• Collaborative team player who fosters knowledge sharing and mentorship
• Effective communicator, capable of translating technical concepts to diverse audiences
• Adaptable and proactive, with a passion for continuous learning and innovation
• Customer-focused, with a commitment to delivering high-quality solutions on time
• Self-driven, organized, and able to manage multiple priorities in a fast-paced environment

Experience Level: senior Employment Type: full-time Workplace Type: onsite Category: Engineering Industry: Technology Salary Range: Not stated Salary Min: Not stated Salary Max: Not stated Salary Currency: USD Salary Period: year Required Skills: IC Validator, Calibre, Pegasus, Perl, Tcl, Python, CMOS layout, ASIC design flows, foundry process requirements Preferred Skills: None

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are an experienced analog design engineer, passionate about developing cutting-edge SerDes products and advancing high-speed chip-to-chip communications. With a strong grasp of CMOS technologies, you possess a solid background in analog and mixed-signal block design, particularly related to high-speed interfaces such as Drivers, Receivers, Clocking, and CDR. You thrive in collaborative environments, working closely with layout and cross-functional teams to optimize circuit performance, power, and area. Your analytical skills and problem-solving mindset enable you to tackle complex challenges and deliver reliable solutions. You communicate effectively in English, both in writing and verbally, and are comfortable using industry-standard IC design packages and UNIX operating systems. With at least five years of industry experience and a specialization in electronics, you’re eager to make a meaningful impact in industries ranging from mobile and automotive to cloud computing, AI, IoT, 5G, and storage. You value inclusion and diversity and are motivated to contribute to the innovations that power the Era of Smart Everything.

What You’ll Be Doing:

• Develop and/or validate analog circuits considering electrical specifications and reliability constraints.
• Document simulation results.
• Evaluate the impact of parasitic effects related to layout implementations. Work with the layout team to minimize such effects, improving performance, power, and area.
• Define and plan analog design activities.

The Impact You Will Have:

• Enable high-speed communications for leading-edge devices and systems across multiple industries.
• Help optimize circuit performance, power, and area for Synopsys’ silicon-proven SerDes products.
• Support the integration of advanced analog blocks into SoCs to meet unique application requirements.
• Minimize risk and accelerate time-to-market for differentiated customer products.
• Contribute to the continuous improvement of analog design methodologies and processes.
• Collaborate with a global, multicultural team to drive innovation in high-speed interface technologies.

What You’ll Need:

• Good understanding CMOS technologies
• Good analysis, problem-solving and organization skills
• Good working experience in analog and mixed-signal block design, preferably related to high speed SERDES (Drivers, Receivers, SERDES, Clocking, CDR)
• Good written and verbal communication in English
• Familiarity with one or more IC design packages
• Familiarity with UNIX operating Systems

Who You Are:

• Minimum 5-years’ industry experience
• Knowledge of analog CMOS circuit design, typically obtained through a specialization in Electronics (at the University), is preferred

The Team You’ll Be A Part Of:

You will be part of a fast-growing analog and mixed signal R&D team, developing high-speed analog integrated circuits in the most advanced FinFET/GAA process nodes. You’ll interact with a global, dynamic, multi-cultural and cross-functional design team, working together to deliver industry-leading SerDes IP solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Staff Engineer in Analog Design, you will be part of a team focused on developing high-speed SerDes physical interfaces and supporting analog blocks for advanced SoCs. You will work alongside passionate engineers who value technical excellence, innovation, and teamwork - driving the integration of new capabilities for the Era of Smart Everything.

Designing and validating analog and mixed-signal circuits, with a focus on high-speed SerDes interfaces (including drivers, receivers, clocking, PLL, DLL, and CDR). Conducting schematic entry, simulation, and final validation of analog blocks, from basic reference components to complex analog front-ends. Collaborating with layout engineers to review and optimize layout designs, minimizing the impact of parasitics on circuit performance. Developing and validating custom digital circuits for high-speed applications, ensuring timing closure and constraint checks using industry standard tools such as Primetime and Nanotime. Utilizing IC design tools and SPICE simulators for simulation, verification, and performance analysis of analog circuits. Engaging with international teams to share knowledge, solve problems, and drive innovation in analog design methodologies.

Key responsibilities include: Designing and validating analog and mixed-signal circuits Conducting schematic entry, simulation, and final validation of analog blocks Collaborating with layout engineers to review and optimize layout designs Developing and validating custom digital circuits Utilizing IC design tools and SPICE simulators Engaging with international teams

The ideal candidate will have: MSc in Electrical or Computer Engineering (or equivalent) with a solid background in transistor-level circuit design 5+ years of hands-on experience in analog circuit design, especially in high-speed mixed-signal environments Strong knowledge of deep submicron CMOS technologies and their application in modern ICs Experience with SPICE simulators, simulation methods, and verification tools for analog circuit analysis Familiarity with industry standard IC design tools and digital circuit validation, including STA timing closure (Primetime, Nanotime, or equivalent) Preferred: Knowledge of Synopsys EDA tools and familiarity with Unix and scripting languages (TCL, Python)

As a Staff Engineer, you will be responsible for delivering high-quality designs, collaborating with cross-functional teams, and driving innovation in analog design methodologies. You will also be expected to mentor junior engineers and contribute to the development of new design techniques and tools.

If you are a motivated and experienced analog design engineer looking to take your career to the next level, we encourage you to apply for this exciting opportunity.

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Job Description

As an Analog Mixed-Signal Engineer at Synopsys, you will be responsible for designing and developing high-performance memory interface solutions that power next-generation technologies. You will work closely with cross-functional teams to meet complex design specifications and project goals.

Responsibilities

• Design and develop DDR/HBM Memory Interface I/O circuits, including GPIO and special I/Os, ensuring robust performance and reliability.
• Collaborate closely with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project milestones.
• Execute circuit design tasks with a focus on quality, efficiency, and adherence to industry standards.
• Apply deep knowledge of CMOS processes and analog/mixed-signal circuitry to innovate and refine design methodologies.
• Review and optimize circuit layouts, ensuring compliance with ESD and JEDEC standards for DDR interfaces.
• Participate in design reviews, provide technical input, and contribute to the continuous improvement of design flows and best practices.
• Document design processes, test plans, and results, supporting knowledge sharing and future project success.

Impact

• Drive the development of high-performance memory interface solutions that power next-generation technologies.
• Enhance the robustness and reliability of Synopsys' analog and mixed-signal IP portfolio.
• Ensure products meet or exceed industry standards, supporting customer success and market leadership.
• Influence cross-functional teams by sharing insights and best practices in circuit design and layout.
• Contribute to the delivery of cutting-edge silicon solutions for global semiconductor leaders.
• Support continuous innovation, helping Synopsys stay ahead in a competitive, fast-moving industry.

Requirements

• BTech/MTech in Electronics or Electrical Engineering.
• 1–3 years of experience in analog/mixed-signal circuit design, with expertise in CMOS processes and deep submicron technologies.
• Proficiency in CMOS circuit design and layout methodologies; experience with ESD concepts is a plus.
• Familiarity with ASIC design flows and JEDEC DDR interface requirements, including DDR Timing, ODT, and SDRAM functionality.
• Ability to work with cross-disciplinary teams to meet complex design specifications and project goals.

Team

You will join a world-class engineering team focused on analog and mixed-signal IP development for cutting-edge memory interfaces. Our team thrives on innovation, collaboration, and technical excellence, working closely with global experts to deliver industry-leading solutions for top-tier semiconductor clients. We foster an inclusive and supportive culture where every member's contributions are valued and professional growth is encouraged.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are: You are a visionary and detail-oriented principal engineer, passionate about pushing the boundaries of analog circuit design in high-speed interfaces. With a deep technical foundation and proven leadership skills, you thrive in collaborative environments and are eager to mentor the next generation of engineers.

Your expertise in SerDes and analog macros enables you to dissect complex architectural requirements and translate them into robust, scalable designs. You are adept at balancing power, area, and performance trade-offs, and you proactively seek innovative solutions to technical challenges.

What You’ll Be Doing:

• Own the architecture, design, and implementation of analog macro-level circuits for SerDes IP.
• Track and review the technical progress of sub-block owners, ensuring alignment with project goals.
• Interpret SerDes standards and architecture documents to develop detailed analog specifications.
• Identify and refine circuit implementations, optimizing for power, area, and performance targets.
• Propose and execute design and verification strategies using advanced simulator features for robust outcomes.
• Oversee physical layout to minimize parasitics, device stress, and process variation impacts.
• Collaborate closely with digital RTL engineers on calibration, adaptation, and control algorithms for analog circuits.
• Present simulation data and technical insights for peer and customer reviews.
• Mentor and review the progress of junior engineers, fostering growth and technical excellence.
• Document design features, methodologies, and test plans for internal and customer use.
• Consult on electrical characterization and testing of circuits within the SerDes IP product portfolio.

The Impact You Will Have:

• Drive innovation and quality in Synopsys’ industry-leading SerDes IP solutions.
• Elevate the performance and reliability of analog designs, enabling next-generation connectivity standards.
• Contribute to the success of global customers by delivering robust, silicon-proven analog macros.
• Enhance cross-functional collaboration across design, layout, and digital teams.
• Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.
• Influence the direction of advanced analog design methodologies and verification strategies.
• Provide technical leadership in customer engagements and peer reviews.
• Support continuous improvement in design processes and documentation practices.

What You’ll Need:

• PhD with 7+ years, or MSc with 10+ years of SerDes/high-speed analog design experience.
• Expertise in transistor-level circuit design and strong CMOS design fundamentals.
• Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.
• Leadership experience in guiding small teams through macro-level design projects.
• In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
• Advanced skills in optimizing FinFET CMOS layouts to minimize parasitics and local device mismatches.
• Awareness of ESD and reliability issues, including circuit techniques and layout strategies.
• Proficiency with EDA tools for schematic entry, physical layout, and design verification.
• Experience with SPICE simulators for detailed circuit analysis.
• Familiarity with analog behavioral modeling and simulation control using Verilog-A.
• Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.

Who You Are:

• Analytical thinker with exceptional problem-solving skills.
• Collaborative leader and effective communicator.
• Detail-oriented and methodical in approach.
• Adaptable and open to learning new technologies.
• Mentor and role model for junior engineers.
• Self-motivated and proactive in driving project outcomes.
• Committed to excellence, reliability, and innovation.

The Team You’ll Be A Part Of: You will join a dynamic and multidisciplinary team of analog, digital, and mixed-signal engineers dedicated to developing industry-leading SerDes IP solutions. The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products. Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Layout Design Senior Engineer, you will develop high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below). You will design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements.

Responsibilities:

• Develop high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below)
• Design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements
• Perform DRC, LVS, ERC, Antenna checks, and ensure timely completion of verification cycles
• Apply layout matching techniques and address ESD, latch-up, EMIR, DFM, and LEF generation issues
• Collaborate closely with cross-disciplinary teams to optimize layout for performance, power, and area
• Troubleshoot and debug layout challenges, continually improving methodologies and design outcomes
• Document design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement

Impact:

• Accelerate the integration of advanced silicon IP into customer SoCs, enabling rapid time-to-market with differentiated products
• Ensure robust and reliable IP performance through meticulous layout design and physical verification
• Drive innovation in memory interface IPs, supporting the demands of AI, cloud computing, IoT, and more
• Contribute to the world's broadest portfolio of silicon IP, enhancing Synopsys' position as a technology leader
• Reduce risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements
• Foster a culture of collaboration, accountability, and technical excellence within the team and across the organization
• Help shape the next wave of semiconductor advancements, powering smart devices and connected systems globally

Requirements:

• B.Tech/M.Tech degree in Electronics, Electrical, or related engineering discipline
• 2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below)
• Expertise in DRC, LVS, ERC, Antenna checks, and physical verification methodologies
• Strong understanding of deep submicron effects, floorplan techniques, and layout matching in CMOS, FinFET, GAA technologies
• Experience with ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation
• Proficiency with layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar EDA platforms
• Ability to work independently and collaboratively, managing multiple tasks and priorities

Team:

You will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR & HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world's most advanced chips and devices.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a highly skilled A&MS Design Staff Engineer, you will lead the design of analog and mixed-signal circuits, blocks, and subsystems. You will develop architecture proposals and evaluate design tradeoffs for performance, power, area, and cost. You will perform circuit simulation, verification, and optimization using industry-standard EDA tools. You will support tape-out activities, silicon bring-up, debug, and characterization. You will collaborate with layout engineers to ensure design intent, robustness, and manufacturability. You will define and execute validation plans to meet product requirements. You will review design specifications, schematics, and test results. You will mentor junior engineers and contribute technical leadership across projects. You will work closely with system, digital, validation, and product teams to resolve technical issues. You will drive continuous improvement in design methodologies and best practices.

Key responsibilities include:

• Leading the design of analog and mixed-signal circuits, blocks, and subsystems
• Developing architecture proposals and evaluating design tradeoffs for performance, power, area, and cost
• Performing circuit simulation, verification, and optimization using industry-standard EDA tools
• Supporting tape-out activities, silicon bring-up, debug, and characterization
• Collaborating with layout engineers to ensure design intent, robustness, and manufacturability
• Defining and executing validation plans to meet product requirements
• Reviewing design specifications, schematics, and test results
• Mentoring junior engineers and contributing technical leadership across projects
• Working closely with system, digital, validation, and product teams to resolve technical issues
• Driving continuous improvement in design methodologies and best practices

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As a High-Speed Interface Analog Design Engineer, you will develop and/or validate analog circuits considering electrical specifications and reliability constraints. You will document simulation results, evaluate the impact of parasitic effects related to layout implementations, and work with the layout team to minimize such effects, improving performance, power, and area. You will also define and plan analog design activities.

You will enable high-speed communications for leading-edge devices and systems across multiple industries. You will help optimize circuit performance, power, and area for Synopsys' silicon-proven SerDes products. You will support the integration of advanced analog blocks into SoCs to meet unique application requirements. You will minimize risk and accelerate time-to-market for differentiated customer products. You will contribute to the continuous improvement of analog design methodologies and processes. You will collaborate with a global, multicultural team to drive innovation in high-speed interface technologies.

You will be part of a fast-growing analog and mixed signal R&D team, developing high-speed analog integrated circuits in the most advanced FinFET/GAA process nodes. You will interact with a global, dynamic, multi-cultural and cross-functional design team, working together to deliver industry-leading SerDes IP solutions.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a passionate and detail-oriented engineer who thrives on solving complex technical challenges. Your expertise in analog and mixed-signal circuit design is matched by your drive to push the boundaries of data transmission speeds. You enjoy collaborating with multidisciplinary teams and value open communication, ensuring your designs are robust and reliable.

You take pride in your analytical skills, always striving for precision and innovation, and you approach every project with curiosity and a growth mindset. Whether you are a Senior or Staff Engineer, you are ready to take ownership of high-performance SERDES designs, contribute to architecture discussions, and deliver solutions that advance the state of the art.

You will design, simulate, and verify high-speed SERDES TX and RX analog circuits for data rates up to and beyond 200 Gbps. You will develop and optimize SERDES building blocks, including high-speed transmit drivers, receiver front-end circuits, and equalization circuits such as CTLE and DFE.

You will perform detailed schematic-level analysis and simulations across process, voltage, and temperature (PVT) corners. You will collaborate closely with layout engineers to ensure proper parasitic control, matching, and signal integrity.

You will run post-layout simulations and support design sign-off for robust silicon implementation. You will participate in design reviews, architecture discussions, and collaborate with digital, system, and validation teams for full SERDES integration.

You will support silicon bring-up, debugging, and correlation with lab measurements for performance validation. You will contribute to design documentation, methodology development, and continuous IP quality improvements.

Delivering high-performance SERDES IP that enables next-generation connectivity solutions across industries.

Advancing the capabilities of high-speed data transmission in advanced CMOS process technologies.

Ensuring robust and silicon-proven analog designs that drive product reliability and customer satisfaction.

Improving design methodologies and contributing to industry-leading IP quality standards.

Facilitating seamless integration of analog and digital subsystems for optimized system performance.

Providing critical support in silicon validation, enabling rapid time-to-market for new products.

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As a Staff Engineer in Analog Design, you will be part of a fast-growing team dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. You will design and develop medium complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards.

Key Responsibilities:

• Design and develop medium complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards.
• Define and plan analog design activities, setting clear milestones and deliverables for project success.
• Prepare and conduct technical design reviews, identifying improvements, tracking actions, and ensuring best practices are followed.
• Evaluate and minimize the impact of layout parasitic effects by collaborating closely with layout teams, optimizing circuit performance, power, and area.
• Perform silicon correlation with simulation results, analyzing discrepancies and driving design refinements.

Impact:

• Accelerate the development of industry-leading SerDes IP products, supporting diverse markets such as mobile, automotive, cloud computing, HPC, AI, IoT, 5G, and storage, enabling high-speed chip-to-chip communications in next-generation devices.
• Enhance Synopsys' reputation as a provider of silicon-proven IP by delivering reliable, high-performance analog designs.
• Reduce risk for customers by ensuring robust correlation between simulation and silicon, leading to differentiated products in the marketplace.
• Foster innovation and continuous improvement within the analog and mixed-signal R&D team, setting benchmarks for technical excellence.

Requirements:

• M.Sc. degree in Electrical Engineering with 3+ years of experience, or Ph.D. in Electrical Engineering with 1.5+ years of experience.
• Background in CMOS analog circuit design, preferably including ADC, DAC, PLL, Rx, Tx, References, or related areas.
• Familiarity with industry-standard IC design packages and EDA tools.
• Experience working in UNIX operating systems.
• Good written and verbal communication skills in English.
• System-level knowledge of SerDes architecture is a plus.

Team:

You will join Synopsys' fast-growing analog and mixed-signal R&D team, dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. The team is global, dynamic, and cross-functional, working collaboratively to deliver world-class products that power innovations across multiple industries.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR & HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification.

Developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below) Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements. Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles. Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues. Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes. Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.

Accelerating the integration of advanced silicon IP into customer SoCs, enabling rapid time-to-market with differentiated products. Ensuring robust and reliable IP performance through meticulous layout design and physical verification. Driving innovation in memory interface IPs, supporting the demands of AI, cloud computing, IoT, and more. Contributing to the world’s broadest portfolio of silicon IP, enhancing Synopsys’ position as a technology leader. Reducing risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements. Fostering a culture of collaboration, accountability, and technical excellence within the team and across the organization. Helping shape the next wave of semiconductor advancements, powering smart devices and connected systems globally.

BTech/MTech degree in Electronics, Electrical, or related engineering discipline. 2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below). Expertise in DRC, LVS, ERC, Antenna checks, and physical verification methodologies. Strong understanding of deep submicron effects, floorplan techniques, and layout matching in CMOS, FinFET, GAA technologies. Experience with ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation. Proficiency with layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar EDA platforms. Ability to work independently and collaboratively, managing multiple tasks and priorities.

Analytical thinker with strong problem-solving and debugging skills. Self-motivated, accountable, and results-driven. Collaborative team player who fosters trust and open communication. Adaptable and eager to learn new technologies and methodologies. Effective communicator with excellent interpersonal skills. Committed to diversity, inclusion, and continuous improvement.

You will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR & HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world’s most advanced chips and devices.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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You are a skilled and motivated analog design engineer, passionate about developing advanced integrated circuits for high-speed communication systems. With a good understanding of CMOS technologies and track record in designing medium complexity analog circuits, you thrive in fast-paced, collaborative environments. You have expertise in some analog functions such as ADCs, DACs, PLLs, and transceiver blocks, and you are adept at delivering robust designs that meet stringent electrical specifications and reliability constraints. Analytical and detail-oriented, you know how to evaluate the impact of layout parasitics and optimizing for performance, power, and area.

You are comfortable conducting technical reviews, planning design activities, and ensuring that silicon results correlate closely with simulation predictions. Your communication skills enable you to interact effectively within a global and multi-cultural team, and your organizational abilities ensure timely delivery of milestones. You are proactive in problem-solving and continuous improvement, and you value mentorship, sometimes guiding junior engineers. Whether you have industry experience or specialized academic training, you are eager to contribute to cutting-edge projects that power innovations in mobile, automotive, cloud, HPC, AI, IoT, 5G, and storage. Inclusivity, diversity, and collaboration are important to you, and you are ready to make a significant impact at Synopsys.

Design and develop medium complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards. Define and plan analog design activities, setting clear milestones and deliverables for project success. Prepare and conduct technical design reviews, identifying improvements, tracking actions, and ensuring best practices are followed. Evaluate and minimize the impact of layout parasitic effects by collaborating closely with layout teams, optimizing circuit performance, power, and area. Perform silicon correlation with simulation results, analyzing discrepancies and driving design refinements. Engage with a global, multi-cultural, and cross-functional R&D team, contributing to a collaborative and innovative work environment.

Accelerate the development of industry-leading SerDes IP products, supporting diverse markets such as mobile, automotive, cloud computing, HPC, AI, IoT, 5G, and storage, enabling high-speed chip-to-chip communications in next-generation devices. Enhance Synopsys' reputation as a provider of silicon-proven IP by delivering reliable, high-performance analog designs. Reduce risk for customers by ensuring robust correlation between simulation and silicon, leading to differentiated products in the marketplace. Foster innovation and continuous improvement within the analog and mixed-signal R&D team, setting benchmarks for technical excellence.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are an experienced layout design engineer with a passion for technological advancement and an eye for detail. You thrive in collaborative, fast-paced environments and are motivated by the challenge of developing next-generation DDR and HBM PHY IPs. With over five years of hands-on experience in layout development, you are adept at navigating complex process technologies such as CMOS, FinFET, and GAA at 7nm and below. You are a natural leader, capable of mentoring junior engineers, driving project execution, and ensuring the highest standards of product quality. Your expertise spans floorplanning, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO frame requirements. You understand the importance of customer requirements at the PHY level and are committed to delivering differentiated solutions that help customers meet their unique performance, power, and size targets. Your communication skills,both written and verbal,are exceptional, enabling you to foster accountability and ownership within cross-functional teams. Above all, you value inclusion, diversity, and continuous learning, and are eager to contribute to a workplace that celebrates innovative thinking and collaboration.

What You’ll Be Doing:

• Leading the development of cutting-edge DDR and HBM layout IPs, setting technical direction and standards.
• Providing hands-on expertise in layout creation, problem-solving, and technical troubleshooting.
• Mentoring and guiding junior engineers, fostering growth and technical excellence within the team.
• Estimating project efforts, planning schedules, and executing projects in cross-functional settings.
• Collaborating with teams to support critical layout requirements, floorplanning, and quality assurance processes.
• Conducting layout reviews, ensuring compliance with release processes, and meeting stringent customer requirements.

The Impact You Will Have:

• Accelerate the integration of advanced silicon IP in SoCs, driving innovation in smart devices and systems.
• Enhance product differentiation and performance, enabling customers to meet demanding market requirements.
• Reduce time-to-market and risk for customers through robust layout design and technical leadership.
• Support Synopsys’ reputation as a leader in DDR & HBM PHY IP development, contributing to industry benchmarks.
• Foster an inclusive and collaborative engineering culture that values accountability and technical excellence.
• Mentor and develop the next generation of layout engineers, ensuring sustained innovation and talent growth.

What You’ll Need:

• BTech/MTech in Electronics, Electrical Engineering, or related field.
• 5+ years of relevant experience in layout design, preferably in DDR & HBM PHY IP development.
• Deep understanding of submicron effects, floorplan techniques in CMOS, FinFET, GAA technologies (7nm and below).
• Expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.
• Strong ability to lead projects, manage schedules, and ensure product quality within tight timelines.
• Excellent written, verbal communication, and interpersonal skills.

Who You Are:

• Innovative thinker with a proactive approach to problem-solving.
• Effective communicator and collaborator across diverse teams.
• Detail-oriented, accountable, and committed to high standards of quality.
• Mentor and leader, fostering growth and technical excellence.
• Adaptable, eager to learn, and open to new ideas and technologies.
• Champion for inclusion, diversity, and teamwork.

The Team You’ll Be A Part Of: You will join a dynamic Silicon IP team focused on developing high-performance DDR and HBM PHY IPs. Our team values technical innovation, collaborative problem-solving, and continuous improvement. We work closely with cross-functional groups including design, verification, and customer support to deliver industry-leading solutions that shape the future of smart technology.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are an experienced layout design engineer with a passion for technological advancement and an eye for detail. You thrive in collaborative, fast-paced environments and are motivated by the challenge of developing next-generation DDR and HBM PHY IPs. With over five years of hands-on experience in layout development, you are adept at navigating complex process technologies such as CMOS, FinFET, and GAA at 7nm and below. You are a natural leader, capable of mentoring junior engineers, driving project execution, and ensuring the highest standards of product quality. Your expertise spans floorplanning, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO frame requirements. You understand the importance of customer requirements at the PHY level and are committed to delivering differentiated solutions that help customers meet their unique performance, power, and size targets. Your communication skills,both written and verbal,are exceptional, enabling you to foster accountability and ownership within cross-functional teams. Above all, you value inclusion, diversity, and continuous learning, and are eager to contribute to a workplace that celebrates innovative thinking and collaboration.

Leading the development of cutting-edge DDR and HBM layout IPs, setting technical direction and standards. Providing hands-on expertise in layout creation, problem-solving, and technical troubleshooting. Mentoring and guiding junior engineers, fostering growth and technical excellence within the team. Estimating project efforts, planning schedules, and executing projects in cross-functional settings. Collaborating with teams to support critical layout requirements, floorplanning, and quality assurance processes. Conducting layout reviews, ensuring compliance with release processes, and meeting stringent customer requirements.

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Your responsibilities will include applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries. You will collaborate with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.

You will conduct design reviews and offer constructive feedback to enhance quality and performance. You will utilize Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.

The impact you will have includes accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions, ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products, enhancing productivity and efficiency through workflow automation and quality assurance initiatives, driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA, fostering collaboration across global teams, leading to improved methodologies and best practices, and maintaining the highest standards of quality, compliance, and performance in every design delivered.

To succeed in this role, you will need a BTech/MTech in Electrical Engineering, Electronics, or related field, with 5+ years of relevant experience in IC layout design, preferably in standard cell libraries. You will require proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM), hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs, strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting, solid understanding of sign-off flow, waiver handling, and quality tracking, excellent written and spoken English for technical communication, deep knowledge of CMOS, DPT, EM/IR, ESD/latch-up, noise, and digital layout fundamentals, and ability to work independently and collaborate effectively across teams.

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You will be comfortable conducting technical reviews, planning design activities, and ensuring that silicon results correlate closely with simulation predictions. Your communication skills will enable you to interact effectively within a global and multi-cultural team, and your organizational abilities will ensure timely delivery of milestones. You will be proactive in problem-solving and continuous improvement, and you will value mentorship, sometimes guiding junior engineers.

You will join Synopsys' fast-growing analog and mixed-signal R&D team, dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. The team is global, dynamic, and cross-functional, working collaboratively to deliver world-class products that power innovations across multiple industries.

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As an experienced analog design engineer, you will be responsible for driving the design and development of medium to large complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards. You will guide analog designers to ensure designs meet electrical specifications and reliability constraints. You will also define methods and procedures for project execution, including planning analog design activities and associated milestones.

You will conduct and prepare design reviews, following up on improvements, and ensuring high quality outcomes. You will evaluate and minimize parasitic effects related to layout implementations, collaborating with layout teams to optimize performance, power, and area. You will ensure silicon correlation with simulation results, validating design accuracy and robustness.

You will mentor and train less experienced analog designers, fostering skill development within the team. You will engage with a global, multi-cultural, and cross-functional R&D team, contributing to a collaborative and innovative work environment.

The successful candidate will have a proven track record in CMOS analog design, preferably including hands-on experience with ADC, DAC, PLL, Rx, Tx, References, etc. They will have experience coordinating design activities across teams and managing medium complexity designs. They will be familiar with industry-standard IC design packages and EDA tools.

The ideal candidate will be a collaborative team player who thrives in multicultural, global environments. They will be an analytical thinker with strong problem-solving and organizational skills. They will be an effective communicator, able to lead reviews and share knowledge clearly.

The team you will be a part of is Synopsys' fast-growing analog and mixed-signal R&D team, dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. The team is global, dynamic, and cross-functional, working collaboratively to deliver world-class products that power innovations across multiple industries.

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As a leader, you are motivated by mentoring and elevating your team, fostering a collaborative environment that encourages knowledge sharing and accountability. You are comfortable handling multi-faceted projects, from initial floorplanning to the final tape-out, and you have a proven ability to manage schedules, estimate efforts, and deliver best-in-class products on time.

Your expertise spans across layout matching techniques, ESD protection, DFM, and advanced verification methodologies, enabling you to anticipate and solve complex challenges. You are recognised for your strong communication skills, both written and verbal, and you know how to clearly articulate technical concepts to cross-functional teams and customers alike.

You are inclusive, collaborative, and open-minded, actively seeking diverse perspectives while fostering a supportive team culture. You are accountable and results-driven, with a demonstrated ability to take ownership and deliver on commitments.

You will join a dynamic, high-impact team at the forefront of silicon IP innovation, dedicated to delivering world-class memory interface solutions. Our team thrives on technical excellence, close collaboration, and a shared commitment to pushing the boundaries of what's possible in chip design.

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You are a passionate engineer with a strong foundation in analog and mixed-signal circuit design, eager to make a tangible impact in the world of semiconductor innovation. You thrive in collaborative environments, working alongside diverse teams to solve complex technical challenges. With 1–3 years of experience and a solid academic background in Electronics or Electrical Engineering, you bring a keen understanding of CMOS processes and are adept at navigating deep submicron technologies. Your curiosity drives you to stay current with industry standards, including JEDEC requirements for DDR interfaces, and you are enthusiastic about mastering new methodologies and tools. You value quality and efficiency, consistently delivering robust designs that meet rigorous specifications. Your communication skills enable you to articulate technical concepts clearly and foster productive relationships within cross-functional teams. You are detail-oriented, self-motivated, and embrace opportunities to learn and grow. Whether tackling circuit design tasks or collaborating with system engineers, you demonstrate adaptability, integrity, and a commitment to excellence. Your proactive approach, analytical mindset, and willingness to take initiative make you an invaluable contributor to the team. If you are excited about working on cutting-edge memory interface solutions and contributing to the next generation of high-performance chips, Synopsys is the place for you.

Designing DDR/HBM Memory Interface I/O circuits, including GPIO and Special IOs, ensuring optimal performance and reliability. Collaborating with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project goals. Executing circuit design tasks with a focus on quality, efficiency, and adherence to industry standards. Developing and refining analog/mixed signal circuitry, leveraging advanced CMOS technologies and layout methodologies. Contributing to the ASIC design flow, from concept to implementation, including verification and documentation. Communicating effectively with internal development teams, providing technical insights and feedback throughout the design process. Participating in design reviews, troubleshooting, and optimization activities to ensure robust and scalable solutions.

Accelerate the development of high-performance memory interfaces, integral to next-generation computing platforms. Enhance product quality and reliability by applying best practices in analog circuit design and layout. Drive innovation in deep submicron CMOS technologies, enabling advanced chip functionalities. Contribute to Synopsys’ leadership in DDR/HBM IP solutions, helping customers achieve breakthrough results. Foster a culture of collaboration and technical excellence across multidisciplinary teams. Support the delivery of robust, standards-compliant IP that powers industry-leading silicon solutions. Enable seamless integration and performance optimization for customers worldwide.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience,primarily in Physical Verification (PV),you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

What You'll Be Doing:

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies. Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python. Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions. Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team. Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys' technical edge.

The Impact You Will Have:

Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. Contribute to the development of next-generation verification methodologies and best practices within Synopsys. Strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

What You'll Need:

B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field. 8-10 years of hands-on experience in the Physical Verification (PV) domain. Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS. Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development. Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements. Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks. Exposure to competitive EDA tools and awareness of their strengths and limitations.

Who You Are:

An analytical thinker with strong problem-solving abilities and meticulous attention to detail. A collaborative team player who fosters knowledge sharing and mentorship. Effective communicator, capable of translating technical concepts to diverse audiences. Adaptable and proactive, with a passion for continuous learning and innovation. Customer-focused, with a commitment to delivering high-quality solutions on time. Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

The Team You'll Be A Part Of:

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You'll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You Are: You are a passionate engineer with a strong foundation in analog and mixed-signal circuit design, eager to make a tangible impact in the world of semiconductor innovation. You thrive in collaborative environments, working alongside diverse teams to solve complex technical challenges. With 2+yrs experience and a solid academic background in Electronics or Electrical Engineering, you bring a keen understanding of CMOS processes and are adept at navigating deep submicron technologies.

What You'll Be Doing: Designing DDR/HBM Memory Interface I/O circuits, including GPIO and Special IOs, ensuring optimal performance and reliability. Collaborating with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project goals. Executing circuit design tasks with a focus on quality, efficiency, and adherence to industry standards. Developing and refining analog/mixed signal circuitry, leveraging advanced CMOS technologies and layout methodologies. Contributing to the ASIC design flow, from concept to implementation, including verification and documentation. Communicating effectively with internal development teams, providing technical insights and feedback throughout the design process. Participating in design reviews, troubleshooting, and optimization activities to ensure robust and scalable solutions.

The Impact You Will Have: Accelerate the development of high-performance memory interfaces, integral to next-generation computing platforms. Enhance product quality and reliability by applying best practices in analog circuit design and layout. Drive innovation in deep submicron CMOS technologies, enabling advanced chip functionalities. Contribute to Synopsys' leadership in DDR/HBM IP solutions, helping customers achieve breakthrough results. Foster a culture of collaboration and technical excellence across multidisciplinary teams. Support the delivery of robust, standards-compliant IP that powers industry-leading silicon solutions. Enable seamless integration and performance optimization for customers worldwide.

What You'll Need: B.Tech/M.Tech degree in Electronics or Electrical Engineering. 2+ years of hands-on experience in CMOS circuit design, preferably with exposure to deep submicron process technologies. Proficiency in analog/mixed signal design methodologies and layout flows. Familiarity with JEDEC DDR interface requirements, DDR Timing, ODT, and SDRAM functionality is a strong plus. Basic understanding of ESD concepts and ASIC design flow. Demonstrated ability to execute assigned circuit design tasks with high quality and efficiency. Strong written and verbal communication skills for effective team interactions.

Who You Are: Analytical thinker with strong problem-solving skills. Collaborative and adaptable, thriving in dynamic team settings. Detail-oriented and quality-driven, with a commitment to excellence. Proactive, self-motivated, and eager to learn new technologies. Effective communicator, capable of conveying technical concepts clearly. Resilient and resourceful, able to navigate complex challenges.

The Team You'll Be A Part Of: You will join a highly skilled engineering team specializing in DR I/O circuit design for memory interfaces. The team is focused on developing innovative DDR/HBM solutions, collaborating closely with PHY, package, and system engineers. Together, you will drive advancements in chip performance, reliability, and integration, shaping the future of semiconductor technology.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR & HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification.

You will develop high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below). You will design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements.

You will apply layout matching techniques and address ESD, latch-up, EMIR, DFM, and LEF generation issues. You will collaborate closely with cross-disciplinary teams to optimize layout for performance, power, and area.

You will troubleshoot and debug layout challenges, continually improving methodologies and design outcomes. You will document design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.

Accelerating the integration of advanced silicon IP into customer SoCs, ensuring robust and reliable IP performance through meticulous layout design and physical verification, driving innovation in memory interface IPs, and reducing risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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Our team is focused on developing innovative DDR/HBM solutions, collaborating closely with PHY, package, and system engineers. Together, you will drive advancements in chip performance, reliability, and integration, shaping the future of semiconductor technology.

Key Responsibilities:

• Designing DDR/HBM Memory Interface I/O circuits, including GPIO and Special IOs, ensuring optimal performance and reliability.
• Collaborating with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project goals.
• Executing circuit design tasks with a focus on quality, efficiency, and adherence to industry standards.
• Developing and refining analog/mixed signal circuitry, leveraging advanced CMOS technologies and layout methodologies.
• Contributing to the ASIC design flow, from concept to implementation, including verification and documentation.
• Communicating effectively with internal development teams, providing technical insights and feedback throughout the design process.
• Participating in design reviews, troubleshooting, and optimization activities to ensure robust and scalable solutions.

Requirements:

• B.Tech/M.Tech degree in Electronics or Electrical Engineering.
• 2+ years of hands-on experience in CMOS circuit design, preferably with exposure to deep submicron process technologies.
• Proficiency in analog/mixed signal design methodologies and layout flows.
• Familiarity with JEDEC DDR interface requirements, DDR Timing, ODT, and SDRAM functionality is a strong plus.
• Basic understanding of ESD concepts and ASIC design flow.
• Demonstrated ability to execute assigned circuit design tasks with high quality and efficiency.
• Strong written and verbal communication skills for effective team interactions.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

Experience Level: Senior Employment Type: Full-time Workplace Type: Onsite Category: Engineering Industry: Technology Salary Range: Not stated Salary Min: Not stated Salary Max: Not stated Salary Currency: USD Salary Period: Year Required Skills: CMOS circuit design, analog/mixed signal design methodologies, layout flows, JEDEC DDR interface requirements, DDR Timing, ODT, SDRAM functionality, ESD concepts, ASIC design flow Preferred Skills: Not stated

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You are a passionate engineer with a strong foundation in analog and mixed-signal circuit design, eager to make a meaningful impact through your expertise. With a BTech or MTech and substantial hands-on experience (BTech+5 years / MTech+3 years), you have mastered the nuances of CMOS processes and deep submicron technologies. You enjoy solving complex challenges in DDR I/O circuit design and thrive in collaborative environments where your technical insights drive innovation.

Designing and developing DDR I/O circuits, ensuring robust performance and compliance with industry standards. Collaborating with cross-functional teams on analog and mixed-signal circuit architecture and implementation. Performing circuit simulations, layout reviews, and post-layout analysis to optimize designs for performance and reliability. Integrating ESD protection and addressing deep submicron process challenges in circuit development. Contributing to ASIC design flows and participating in design reviews to ensure quality and manufacturability. Documenting design methodologies, results, and communicating effectively with internal development teams. Interfacing with verification and validation teams to support the testing and debugging of DDR I/O circuits.

Deliver innovative DDR I/O circuit designs that enable high-speed, reliable data transfer in advanced silicon products. Enhance product quality and efficiency through rigorous design practices and attention to detail. Drive the adoption of best practices in CMOS and mixed-signal design across teams. Support Synopsys' leadership in chip design by contributing to differentiated IP solutions. Facilitate faster time-to-market for cutting-edge semiconductor products by ensuring robust design and integration. Mentor and collaborate with junior engineers, fostering a culture of excellence and continuous improvement. Strengthen Synopsys' reputation for technical innovation and reliability in the semiconductor industry.

BTech+5 years or MTech+3 years in Electrical/Electronics Engineering or related discipline. Expertise in CMOS circuit design and layout methodology, with experience in deep submicron process technologies. Understanding of analog/mixed signal circuitry and basic ESD concepts. Familiarity with ASIC design flow and JEDEC DDR interface standards, including DDR Timing, ODT, and SDRAM functionality. Strong skills in executing assigned circuit design tasks efficiently and to the highest quality standards. Proficiency in circuit simulation tools and layout review processes.

Detail-oriented, methodical, and committed to delivering high-quality results. Collaborative and effective in cross-team communication. Adaptable and able to manage multiple priorities in a fast-paced environment. Curious and eager to learn about new technologies and industry trends. Proactive problem-solver with strong analytical skills. Clear communicator, both verbally and in writing.

You will join a dynamic team of analog and mixed-signal engineers focused on developing industry-leading DDR I/O solutions. The team fosters an inclusive culture, values diverse perspectives, and collaborates closely with digital, verification, and layout experts to deliver world-class products. Together, you'll push the boundaries of semiconductor innovation, leveraging collective expertise to solve complex challenges and achieve technical excellence.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Your responsibilities will include:

• Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
• Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.
• Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
• Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.
• Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.
• Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.
• Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys' technical edge.

You will accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. You will ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. You will drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. You will enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. You will contribute to the development of next-generation verification methodologies and best practices within Synopsys. You will strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

To be successful in this role, you will need:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.
• 5-8 years of hands-on experience in the Physical Verification (PV) domain.
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
• Exposure to competitive EDA tools and awareness of their strengths and limitations.

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

Rewards and benefits include a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Sr. Manager of R&D Engineering, you will lead a team of engineers in developing cutting-edge CMOS embedded memory technologies. You will be responsible for designing architecture and circuit implementation for ultra-high-speed, ultra-low-power, or high-density designs. You will also perform schematic entry, circuit simulation, layout planning, and supervision, as well as verify and validate designs to ensure high quality and performance.

The ideal candidate will have a strong background in memory compiler development, with a minimum of 8-10 years of experience in CMOS memory design, circuit simulation, and memory layout design. You will also have experience with layout parasitic extraction and verification tools, as well as programming skills in C-Shell, Perl, C++, or JavaScript.

As a leader, you will be responsible for mentoring and guiding a team of engineers, enhancing workflows and methodologies, and driving project success. You will also be expected to communicate effectively with cross-functional teams, including CAD and Frontend engineers, to automate memory compilers and generate EDA models.

At Synopsys, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Sr Engineer, you will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. You will automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

Responsibilities:

• Develop and validate DRC, LVS, and Fill runsets for the Synopsys IC Validator tool
• Collaborate with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes
• Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python
• Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges
• Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions
• Mentor junior team members, share best practices, and contribute to a knowledge-sharing culture within the team

Impact:

• Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses
• Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market
• Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps
• Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges
• Contribute to the development of next-generation verification methodologies and best practices within Synopsys
• Strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support

Requirements:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field
• 5-8 years of hands-on experience in the Physical Verification (PV) domain
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks
• Exposure to competitive EDA tools and awareness of their strengths and limitations

Who You Are:

• An analytical thinker with strong problem-solving abilities and meticulous attention to detail
• A collaborative team player who fosters knowledge sharing and mentorship
• Effective communicator, capable of translating technical concepts to diverse audiences
• Adaptable and proactive, with a passion for continuous learning and innovation
• Customer-focused, with a commitment to delivering high-quality solutions on time
• Self-driven, organized, and able to manage multiple priorities in a fast-paced environment

The Team You’ll Be A Part Of:

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You are a visionary and detail-oriented principal engineer, passionate about pushing the boundaries of analog circuit design in high-speed interfaces.

With a deep technical foundation and proven leadership skills, you thrive in collaborative environments and are eager to mentor the next generation of engineers.

Your expertise in SerDes and analog macros enables you to dissect complex architectural requirements and translate them into robust, scalable designs.

You are adept at balancing power, area, and performance trade-offs, and you proactively seek innovative solutions to technical challenges.

Your experience spans both the theoretical and practical aspects of circuit design,from transistor-level fundamentals to silicon-proven implementations.

You champion rigorous verification methodologies and leverage advanced simulation tools to ensure the highest quality outcomes.

As a communicator, you clearly articulate your ideas to peers, customers, and junior team members, fostering a culture of learning and excellence.

You are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you approach every project with a commitment to reliability, efficiency, and continuous improvement.

Your adaptability and curiosity make you a valuable contributor to cross-functional teams, and you are excited to make a lasting impact at Synopsys.

Own the architecture, design, and implementation of analog macro-level circuits for SerDes IP.

Track and review the technical progress of sub-block owners, ensuring alignment with project goals.

Interpret SerDes standards and architecture documents to develop detailed analog specifications.

Identify and refine circuit implementations, optimizing for power, area, and performance targets.

Propose and execute design and verification strategies using advanced simulator features for robust outcomes.

Oversee physical layout to minimize parasitics, device stress, and process variation impacts.

Collaborate closely with digital RTL engineers on calibration, adaptation, and control algorithms for analog circuits.

Present simulation data and technical insights for peer and customer reviews.

Mentor and review the progress of junior engineers, fostering growth and technical excellence.

Document design features, methodologies, and test plans for internal and customer use.

Consult on electrical characterization and testing of circuits within the SerDes IP product portfolio.

Drive innovation and quality in Synopsys’ industry-leading SerDes IP solutions.

Elevate the performance and reliability of analog designs, enabling next-generation connectivity standards.

Contribute to the success of global customers by delivering robust, silicon-proven analog macros.

Enhance cross-functional collaboration across design, layout, and digital teams.

Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.

Influence the direction of advanced analog design methodologies and verification strategies.

Provide technical leadership in customer engagements and peer reviews.

Support continuous improvement in design processes and documentation practices.

PhD with 7+ years, or MSc with 10+ years of SerDes/high-speed analog design experience.

Expertise in transistor-level circuit design and strong CMOS design fundamentals.

Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.

Leadership experience in guiding small teams through macro-level design projects.

In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.

Advanced skills in optimizing FinFET CMOS layouts to minimize parasitics and local device mismatches.

Awareness of ESD and reliability issues, including circuit techniques and layout strategies.

Proficiency with EDA tools for schematic entry, physical layout, and design verification.

Experience with SPICE simulators for detailed circuit analysis.

Familiarity with analog behavioral modeling and simulation control using Verilog-A.

Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.

Analytical thinker with exceptional problem-solving skills.

Collaborative leader and effective communicator.

Detail-oriented and methodical in approach.

Adaptable and open to learning new technologies.

Mentor and role model for junior engineers.

Self-motivated and proactive in driving project outcomes.

Committed to excellence, reliability, and innovation.

You will join a dynamic and multidisciplinary team of analog, digital, and mixed-signal engineers dedicated to developing industry-leading SerDes IP solutions.

The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products.

Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce.

We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.

Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You will be a part of a fast-growing analog and mixed-signal R&D team, dedicated to developing high-speed analog integrated circuits in the most advanced FinFET/GAA process nodes. You'll interact with a global, dynamic, multi-cultural, and cross-functional design team, collaborating with experts in various fields to create innovative solutions for high-speed communications.

As a Staff Engineer, you will be responsible for:

Developing and/or validating analog circuits considering electrical specifications and reliability constraints. Documenting simulation results and analyzing performance. Evaluating the impact of parasitic effects related to layout implementations and working with the layout team to minimize such effects, improving performance, power, and area. Defining and planning analog design activities for high-speed SerDes products. Collaborating with a global team of engineers to integrate and verify design solutions. Continuously learning and applying the latest advancements in FinFET/GAA process nodes to enhance design efficiency.

You will contribute to the development of high-speed SerDes products that enable high-performance chip-to-chip communications. You will enhance the performance, power efficiency, and reliability of analog integrated circuits in advanced CMOS technologies. You will support the integration of more capabilities into System-on-Chip (SoC) designs, accelerating time-to-market for innovative products.

You will be a part of a dynamic, multicultural, and cross-functional design team, collaborating with experts in various fields to create innovative solutions for high-speed communications.

The ideal candidate will have a good understanding of CMOS technologies and analog circuit design principles. They will have strong analysis, problem-solving, and organizational skills. They will have experience in analog and mixed-signal block design, with a focus on high-speed SERDES. They will be proficient in documenting and analyzing simulation results. They will be familiar with IC design packages and UNIX operating systems.

You will be a collaborative team player who thrives in a global, multicultural environment. You will be an effective communicator with strong written and verbal skills in English. You will be a proactive and self-motivated individual with a passion for innovation and continuous learning. You will be an analytical thinker with the ability to tackle complex design challenges and find creative solutions. You will be a detail-oriented engineer who values precision and accuracy in their work.

You will be rewarded with a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are hiring a Staff Engineer to lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.

As a Staff Engineer, you will be responsible for leading the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies. You will work on hands-on execution of layout development, ensuring precision and adherence to industry standards.

You will also mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.

Estimating project efforts, planning schedules, and executing projects in cross-functional settings will be another key responsibility.

Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks will also be a part of your role.

Managing the release process, ensuring timely delivery and consistent quality of layout deliverables will be your additional responsibility.

Key Responsibilities:

• Lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.

• Hands-on execution of layout development, ensuring precision and adherence to industry standards.

• Mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.

• Estimating project efforts, planning schedules, and executing projects in cross-functional settings.

• Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.

• Managing the release process, ensuring timely delivery and consistent quality of layout deliverables.

Requirements:

• BTech/MTech degree in Electrical Engineering, Electronics, or related field.

• 5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).

• Expertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.

• Strong understanding of floorplan techniques and deep submicron effects.

• Proven ability to lead projects and deliver best product quality within tight timelines.

Preferred Qualifications:

• Collaborative and team-oriented, with a commitment to inclusion and diversity.

• Detail-oriented, with strong problem-solving and analytical skills.

• Effective communicator, both written and verbal, with excellent interpersonal abilities.

• Adaptable and eager to learn, embracing new technologies and methodologies.

• Empathetic mentor, fostering accountability, ownership, and technical growth in others.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.

• In addition to company holidays, we have ETO and FTO Programs.

• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Save for your future with our retirement plans that vary by region and country.

• Competitive salaries.

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As a Layout Design Engineer, you will be designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces. You will collaborate with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.

Responsibilities:

• Designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces.
• Collaborating with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.
• Performing floor planning, layout entry, and comprehensive verification to ensure design quality and compliance with foundry rules.
• Applying advanced techniques to mitigate signal integrity issues, ESD, and latch-up risks, including differential routing, shielding, and substrate biasing.
• Optimizing layouts for reliability, matching, and minimizing parasitic effects such as EM and IR drop.
• Supporting design porting activities to enable seamless migration of layouts across multiple foundry nodes and technology platforms.
• Documenting layout methodologies, best practices, and validation results to support knowledge sharing and continuous improvement.

Requirements:

• Bachelor or advanced degree in Electrical or Computer Engineering (or equivalent) with a solid background in transistor-level design.
• 5+ years of experience in analog and mixed-signal CMOS layout design, including complex integrated circuits.
• Expertise in deep submicron CMOS technologies and layout effects (matching, reliability, proximity, EM, IR, etc.).
• Proficiency in layout floor planning, verification, and quality validation using industry-standard EDA tools.
• Strong knowledge of signal integrity, ESD, and latch-up mitigation techniques.
• Familiarity with UNIX operating systems and scripting languages (TCL, Python) is a plus.
• Experience with Synopsys EDA tools is highly desirable.

Who You Are:

• Detail-oriented and quality-focused, with a commitment to delivering robust and reliable designs.
• Excellent communicator, able to articulate technical concepts clearly to diverse audiences.
• Collaborative team player who builds productive relationships and networks effectively.
• Self-motivated, organized, and able to manage multiple priorities in a dynamic environment.
• Strong problem-solving skills and critical judgment, with a proactive approach to overcoming challenges.
• Adaptable and eager to learn new technologies and methodologies.

The Impact You Will Have:

• Accelerate the development of cutting-edge silicon IP, enabling faster integration of advanced capabilities into SoCs.
• Enhance the performance, reliability, and manufacturability of high-speed interface solutions for next-generation applications.
• Reduce time-to-market and risk for customers by delivering high-quality, validated layout designs.
• Contribute to the innovation of analog and mixed-signal design methodologies within a global team.
• Support the creation of differentiated products that power the Era of Smart Everything, from AI to IoT and beyond.
• Foster a culture of collaboration, knowledge sharing, and technical excellence within the team and across the organization.

The Team You'll Be A Part Of:

You will join a dynamic, international team focused on developing high-speed SerDes physical interfaces and supporting analog blocks for advanced SoC solutions. Our team values innovation, collaboration, and technical excellence, working closely with circuit designers, verification engineers, and global partners to deliver industry-leading silicon IP. We foster a supportive environment where knowledge sharing and continuous learning are encouraged, and where your contributions will directly impact the success of our products and customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned analog design engineer with deep expertise in high-speed SERDES IP. You thrive on solving complex circuit challenges, leading technical initiatives, and collaborating across multidisciplinary teams. Your track record in advanced CMOS design, effective communication skills, and passion for innovation make you a trusted mentor and a key contributor to project and team success.

What You’ll Be Doing:

• Develop and specify SERDES transceiver architectures and sub-blocks based on standards.
• Design, simulate, and verify high-speed analog circuits for optimal power and performance.
• Collaborate with analog, digital, and CAD teams to ensure design quality and efficiency.
• Present technical results internally and externally to customers and industry groups.
• Oversee physical layout to address parasitics and reliability concerns.
• Document features and test plans, and support post-silicon analysis and updates.

The Impact You Will Have:

• Advance industry-leading SERDES IP for next-generation SoCs.
• Enhance product differentiation and customer value.
• Streamline design processes for quality and time-to-market.
• Mentor junior team members and share best practices.
• Influence technical direction and innovation at Synopsys.
• Support customer success and product reliability.

What You’ll Need:

• Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.
• Expertise in transistor-level CMOS design and SERDES sub-circuits.
• Proficiency with schematic, layout, and verification tools; SPICE simulators.
• Experience with scripting languages (Verilog-A, TCL, Python, etc.).
• Strong communication and documentation skills.

Who You Are:

• Technical leader and mentor
• Collaborative and proactive
• Analytical and detail-oriented
• Adaptable and innovative

The Team You’ll Be A Part Of:

A collaborative, high-performing analog and mixed-signal design group focused on developing advanced SERDES IP for leading-edge applications. The core purpose of the team is the development of 224-Gb/s Ethernet SerDes Transceivers for network infrastructure ICs, driving the future of high-speed connectivity in data centers and communications networks for the world.

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You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a visionary leader and seasoned layout design professional, passionate about advancing the frontiers of semiconductor technology. With over eight years of hands-on experience, you thrive in dynamic environments where innovation and technical excellence are paramount.

You possess a deep understanding of deep submicron effects, advanced floorplanning techniques, and process technologies like CMOS, FinFET, and GAA at 7nm and below. Your expertise extends to layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, and IO frame and pitch requirements.

You are adept at leading multi-disciplinary teams, creating an environment of accountability, ownership, and growth, while mentoring junior engineers and empowering senior team members to excel.

You value diversity and inclusion, fostering a culture where every voice is heard and respected. Your collaborative approach ensures seamless cross-functional coordination, and you have a knack for translating complex technical requirements into actionable project plans.

Your communication skills,both written and verbal,enable you to engage effectively with stakeholders at all levels. You are motivated by the opportunity to contribute to high-impact projects, drive innovation in DDR/HBM PHY IP layout, and deliver differentiated products that shape the industry.

If you are ready to lead, inspire, and make a lasting impact, Synopsys is the place for you.

Leading the development of next-generation DDR/HBM IP layouts, driving technical innovation and quality excellence.

Mentoring and managing a team of layout engineers, fostering growth and maximizing individual and team potential.

Developing and maintaining project schedules, ensuring timely delivery while balancing technical and resource constraints.

Collaborating cross-functionally with design, verification, and IP teams to align on project requirements and execution.

Providing subject matter expertise in high-speed DDR/HBM IP layout, including floorplanning, layout reviews, and quality checks.

Executing layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO requirement analysis.

Supporting layout automation through scripting and tool enhancement, optimizing efficiency and productivity.

Acting as an advisor to resolve project challenges and guide teams towards innovative solutions.

Accelerating the integration of advanced capabilities into SoCs, helping customers achieve unique performance, power, and size targets.

Reducing time-to-market and risk for differentiated products through robust layout design and technical leadership.

Driving continuous improvement in layout methodologies and quality standards across cross-functional teams.

Empowering your team to deliver high-performance DDR/HBM PHY IPs that set industry benchmarks.

Fostering a collaborative, inclusive work environment that values innovation, accountability, and diversity.

Contributing to Synopsys’ reputation as the provider of the world’s broadest portfolio of silicon IP.

Shaping the future of chip design and verification technologies through your expertise and leadership.

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As an Analog Design Engineer at Synopsys, you will be designing DDR I/O circuits for high-performance silicon IP, ensuring compliance with industry standards and customer requirements. You will also develop and optimize analog/mixed-signal circuit architectures, focusing on performance, power, and area efficiency.

Key responsibilities include:

• Designing DDR I/O circuits for high-performance silicon IP
• Developing and optimizing analog/mixed-signal circuit architectures
• Executing circuit design tasks using advanced CMOS processes and state-of-the-art layout methodologies
• Collaborating with internal development teams to integrate analog blocks into ASIC and SoC designs
• Assessing and resolving issues related to deep submicron process technologies

The ideal candidate will have a BTech/MTech in Electrical Engineering or related field, with strong knowledge of CMOS processes and deep submicron technology challenges. You should also have hands-on experience with analog/mixed-signal circuit design and layout methodologies, as well as familiarity with ASIC design flow and integration of analog blocks.

At Synopsys, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and detail-oriented engineer who thrives in the fast-paced world of advanced semiconductor layout. You possess a deep understanding of analog and mixed-signal CMOS design principles, with a particular focus on high-speed SerDes interfaces. Your expertise is backed by a solid academic foundation and practical experience, enabling you to tackle complex layout challenges with confidence.

What You’ll Be Doing:

• Drive layout development for high-speed SerDes physical interfaces and complex analog/mixed-signal CMOS blocks.

• Lead the complete layout design process, including floorplanning, verification, and quality assurance, with a strong emphasis on reliability and manufacturability.

• Port designs across multiple foundry nodes, ensuring optimal performance and compliance with technology-specific requirements.

• Implement advanced techniques for signal integrity, ESD, and latch-up mitigation, such as differential routing, shielding, and biasing.

• Collaborate closely with design, verification, and manufacturing teams to deliver robust and scalable layout solutions.

• Utilize Synopsys EDA tools and scripting languages (TCL, Python) to automate layout tasks and optimize workflow efficiency.

The Impact You Will Have:

• Enable Synopsys customers to achieve higher performance and reliability in their silicon designs.

• Accelerate the time-to-market for cutting-edge semiconductor products by delivering high-quality, manufacturable layouts.

• Enhance the robustness and scalability of Synopsys IP through meticulous attention to detail and innovative design solutions.

• Drive advancements in deep submicron CMOS technology adoption and integration.

• Foster a collaborative environment that supports knowledge sharing, mentorship, and professional growth.

• Support Synopsys’ leadership in chip design and verification by contributing to the development of industry-leading IP blocks.

What You’ll Need:

• MSc in Electrical/Computer Engineering (or equivalent).

• Minimum 3 years hands-on experience in analog and mixed-signal CMOS layout, including high-speed SerDes interfaces.

• Deep knowledge of deep submicron CMOS technologies and design for reliability (EM/IR, matching, proximity effects).

• Proficiency in layout floorplanning, porting designs across foundry nodes, and implementing signal integrity and ESD mitigation strategies.

• Experience with custom digital and high-speed digital layout, as well as Synopsys EDA tools.

• Strong skills in UNIX environments, including shell scripting and command-line operations.

• Familiarity with scripting languages such as TCL and Python.

Who You Are:

• Excellent problem-solving, organizational, and communication skills.

• Self-motivated and proactive, with the ability to work independently and as part of a team.

• Effective collaborator who values diverse perspectives and fosters inclusive teamwork.

• Adaptable and open to new challenges, with a commitment to continuous improvement.

• Detail-oriented with a strong sense of ownership and pride in delivering high-quality work.

The Team You’ll Be A Part Of:

You will join a dynamic, highly skilled team dedicated to developing world-class analog and mixed-signal IP for Synopsys’ global customer base. The team is focused on pushing the boundaries of high-speed interface design, reliability, and manufacturability, working together to solve complex challenges and deliver industry-leading solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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big_They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a Staff Engineer in our Analog Design team, you will be responsible for designing and developing full custom analog circuit macros for high-speed SERDES PHY IP.

Your responsibilities will include designing and developing full custom analog circuit macros for high-speed SERDES PHY IP, including transceivers, voltage/current-mode drivers, PLLs, DLLs, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers/deserializers, VCOs, phase interpolators, bandgap references, and clock data recovery circuits.

You will also collaborate with cross-functional teams locally and globally to refine circuit implementations and achieve optimal power, area, and performance targets.

In addition, you will ensure analog sub-block performance adheres to SerDes standards and architecture specification documents.

You will lead verification strategies using advanced simulator features to guarantee the highest quality design outcomes.

You will oversee physical layout processes to minimize parasitic effects, device stress, and process variations.

You will present simulation data for peer and customer reviews, and document design features and test plans.

You will consult on electrical characterization and support the integration of your circuit within the SerDes IP product.

You will handcraft high-performance clock and data paths using digital/CMOS logic cells and verify timing margins with SPICE and STA tools.

You will address ESD and latch-up design verification, crosstalk coupling impacts, and ensure robust mixed-signal analog design.

The impact you will have includes accelerating development of high-performance silicon chips critical to emerging technologies like AI, IoT, and 5G.

You will optimize chip designs for power, cost, and performance, helping customers reduce project schedules by months.

You will advance Synopsys' leadership in high-speed interface IP and mixed-signal design innovation.

You will contribute to the creation of next-generation processes and models for manufacturing advanced chips.

You will support global collaboration, knowledge sharing, and technical excellence across teams and sites.

You will enhance customer satisfaction by delivering reliable, scalable, and high-quality analog IP solutions.

You will drive technical best practices and mentor junior engineers, strengthening the team's capabilities.

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Your responsibilities will include conducting introductory, intermediate, and advanced training sessions for customers, and scoping/delivering professional services projects. You will also gather customer requirements and market trends to inform improvements to Ansys software, collaborate with product development teams to translate feedback into new features, and test new software releases on real-world industrial problems and provide feedback to enhance product performance and usability.

In this role, you will participate in internal initiatives to share knowledge, establish best practices, and develop simulation solutions and FAQs for the knowledge base. You will work closely with customers, sales, and product development to drive innovation and ensure success.

As an Optical Applications Engineer, you will have the opportunity to elevate customer satisfaction and productivity by delivering timely, high-quality technical support and solutions. You will drive adoption of Ansys Lumerical tools and support software revenue growth through expert pre-sales and post-sales engagement. You will empower customers to innovate and validate their designs faster and more accurately with advanced simulation software.

If you are a passionate engineer with a deep understanding of optics and photonics, eager to solve challenging engineering problems and make a significant impact in the industry, we encourage you to apply for this exciting opportunity.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, powering self-driving cars, cloud infrastructure, and learning machines.

You Are:

A Staff-level analog/MS engineer who owns complex designs end-to-end, influences architecture, and mentors others. You balance performance, reliability, and schedule in advanced CMOS and communicate clearly across teams.

If you are excited by the prospect of shaping high-speed connectivity in AI, cloud, automotive, and beyond - and you seek to empower some of the world's most advanced systems - this role is your opportunity to make a meaningful impact.

What You'll Be Doing:

• Taking end-to-end ownership of critical analog and mixed-signal blocks in high-speed SERDES designs
• Making architectural and circuit-level tradeoffs to optimize power, performance, area, and reliability
• Defining, verifying, and documenting testbenches for rigorous pre-silicon validation
• Leading custom analog layout coordination, ensuring parasitic awareness and post-layout optimization
• Driving robustness and quality sign-off processes, including PVT, mismatch, aging, reliability, and yield analysis
• Aligning system-level interfaces and usability considerations for seamless integration
• Executing silicon bring-up, characterization, and correlation against design specifications
• Providing technical leadership, mentorship, and guidance within a collaborative, multidisciplinary team

What You'll Need:

• MS/PhD in Electronics/Computer Engineer or equivalent; typically 7+ years or equivalent Staff-level impact
• Deep analog/MS in deep sub-micron CMOS; signal integrity/noise/jitter
• Proven architecture tradeoffs and production silicon experience
• Strong custom analog layout collaboration; post-layout optimization
• Excellent communication; ability to influence across teams

The Team You'll Be A Part Of:

You will join the IP and System Solutions Group, a cornerstone of Synopsys' mission to enable the industry's most advanced silicon. The SERDES team is renowned for developing high-speed interface IP, deployed across a wide range of applications and technology nodes. This multidisciplinary group collaborates closely to deliver high-performance, power-efficient chips, optimizing power, performance, and area (PPA) while accelerating time-to-market. You'll work alongside experts in architecture, circuit design, layout, and system integration, fostering innovation and excellence in every project.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are seeking an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology.

With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes.

You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus.

Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

You are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements.

As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment.

Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions.

You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.

Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.

Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.

Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.

Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.

Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses.

Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market.

Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps.

Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges.

Contribute to the development of next-generation verification methodologies and best practices within Synopsys.

Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.

5-8 years of hands-on experience in the Physical Verification (PV) domain.

Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.

Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.

Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.

Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.

Exposure to competitive EDA tools and awareness of their strengths and limitations.

An analytical thinker with strong problem-solving abilities and meticulous attention to detail.

A collaborative team player who fosters knowledge sharing and mentorship.

Effective communicator, capable of translating technical concepts to diverse audiences.

Adaptable and proactive, with a passion for continuous learning and innovation.

Customer-focused, with a commitment to delivering high-quality solutions on time.

Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

Join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design.

Work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15231

Remote Eligible

No

Date Posted

02/15/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

• An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL , data converters and SERDES design.

• You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction.

• Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes.

• You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology.

• You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation.

• You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution.

What You’ll Be Doing:

• Leading NRZ/PAM4 Serdes analog design transceiver solutions.

• Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.

• Collaborating with silicon test and debug experts for Sim2Sil correlation.

• Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.

The Impact You Will Have:

• Driving innovation in mixed-signal advanced analog serdes design.

• Enhancing the performance and efficiency of high-speed physical interfaces.

• Contributing to the development of cutting-edge technology in High Speed PHY IP.

• Improving quality and robustness of design through collaboration and Sim2Sil correlation.

What You’ll Need:

• BE 15+ years of relevant experience or MTech 12+ years of relevant experience in mixed signal analog, clock, and datapath circuit design.

• Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.

• Knowledge in Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity .

• Knowledge of RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters

Who You Are:

• Strong fundamentals of CMOS, device physics, and sub-micron design methodologies.

• Experience with PLL designs and high-speed digital circuit design.

• Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques.

• Familiarity with digitally assisted analog circuit techniques.

• Capable to drive technical decision and tradeoff with customer focus

The Team You’ll Be A Part Of:

Join our High-Performance Computing (HPC) Enterprise analog/mixed-signal Serdes team involved in cutting-edge High Speed PHYSICAL Interface Development.

You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

Get an idea of what your daily routine around the office can be like

\ Explore Noida

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15391

Remote Eligible

No

Date Posted

02/23/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ & PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.

You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.

Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.

What You’ll Be Doing:

• Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.

• Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.

• Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.

• Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.

• Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.

• Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.

• Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.

The Impact You Will Have:

• Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.

• Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.

• Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.

• Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.

• Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.

• Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.

What You’ll Need:

• MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).

• Proven expertise with FinFET technologies and CMOS tape-outs.

• Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.

• Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).

• Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.

• Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).

• Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.

• Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.

• Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).

• Excellent communication and documentation skills.

Who You Are:

• Collaborative and open-minded, eager to share knowledge and learn from others.

• Detail-oriented and thorough, with a commitment to delivering high-quality results.

• Analytical thinker with strong problem-solving abilities and a proactive approach.

• Excellent communicator, able to convey complex technical concepts clearly.

• Adaptable and resilient in fast-paced, dynamic environments.

• Committed to fostering an inclusive, innovative, and supportive workplace.

The Team You’ll Be A Part Of:

You’ll join a world-class analog and mixed-signal R&D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What is it like to be an Analog Design Engineer at Synopsys?

Arman Shahmuradyan

Analog Design, Manager

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and patern

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What you'll do

You will be responsible for developing analog sub-block specs based on SerDes standards, refining circuit architectures for optimal power, area, and performance, designing and verifying circuits using advanced simulation tools, collaborating on physical layout to minimize parasitics and variation, presenting simulation data to peers and customers, and documenting design features and test plans.

What you need

• MSc with 5+ years in analog IC design

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What you'll do

• Develop and specify SERDES transceiver architectures and sub-blocks based on standards.
• Design, simulate, and verify high-speed analog circuits for optimal power and performance.

What you need

• Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.

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What you'll do

• Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment.
• Collaborate with cross-functional teams to ensure successful project execution.
• Create and review layout documents to ensure they meet quality standards and are delivered on time.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Minimum 3+ years of experience in Analog and Mixed Signal Circuit Layout.

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What you'll do

Crafting sophisticated layout for mixed signal and analog circuits in deep sub-micron CMOS technologies.

• Reviewing and analyzing floorplans and intricate circuits with circuit designers.

• Running complete sets of design verification tools available on AMS blocks.

• Working with the circuit design team to plan/schedule work and coordinate vital layout tradeoffs as needed.

• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.

• Exceeding engineering specifications and expectations by working closely with the circuit design team.

What you need

• B.Tech/M.Tech with 5+ years of relevant experience.

• Proven experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits.

• Experience in implementing analog layouts to achieve tight matching, low noise, and low power consumption.

• High level of proficiency in custom and standard cell based floor-planning and hierarchical layout assembly.

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What you'll do

• Develop accurate timing models for macros used in multi-die designs.
• Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements.

What you need

• BS/MS in Electronics, Electromechanics, or Telecommunications.
• 5-8 years in analog/mixed signal or custom logic design.

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What you'll do

• Developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.

What you need

• M.Sc. or Ph.D. in Electrical or Computer Engineering.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Expertise in designing high-speed analog CMOS circuits.
• Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.
• Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/systemVerilog.

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What you'll do

• Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
• Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.

What you need

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.
• 5-8 years of hands-on experience in the Physical Verification (PV) domain.
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
• Exposure to competitive EDA tools and awareness of their strengths and limitations.

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What you'll do

• Developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.
• Designing and proposing advanced algorithms to calibrate and adapt transceivers for optimal performance.
• Correlating simulated performance with silicon measurements to ensure accuracy and reliability.
• Providing expert assistance to customers for system-level performance issues and troubleshooting.
• Collaborating with cross-functional teams of analog, digital, and hardware engineers throughout all stages of development.
• Contributing to lab testing and analysis for high-speed serial links, ensuring robust design validation.

What you need

• M.Sc. or Ph.D. in Electrical or Computer Engineering.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Expertise in designing high-speed analog CMOS circuits.
• Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.
• Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/systemVerilog.

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What you'll do

• Reviewing SerDes standards and architecture documents to develop comprehensive analog sub-block specifications.
• Identifying and refining circuit implementations to achieve optimal power, area, and performance targets.
• Proposing and executing design and verification strategies that leverage advanced simulator features for highest-quality design outcomes.

What you need

• BS/BTech degree and 5+ years of experience in IC design, or MS/MTech with 3+ years of experience or PhD degree in a related field.
• In-depth familiarity with transistor-level circuit design and solid CMOS fundamentals.
• Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.

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What you'll do

As a Staff Engineer, you will be responsible for designing and developing advanced embedded memories (SRAM, ROM, Register File).

• Design and develop advanced embedded memories (SRAM, ROM, Register File).
• Lead circuit implementation, simulation, and layout supervision.
• Collaborate with CAD and frontend teams for compiler automation and verification.
• Drivebitcell development and reliability analysis.
• Mentor junior engineers and lead projects.

What you need

• Bachelor’s/Master’s in Electrical Engineering or related field.
• 5-8 years’ experience in embedded CMOS memory design.
• Expertise in SRAM bit cell design, testing, and analysis.
• Proficiency with layout, simulation, and verification tools.
• Programming in C-Shell, Perl; C++/JavaScript a plus.

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What you'll do

Review SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.

Investigate and architect circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.

Collaborate with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.

Oversee and guide the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.

Present and review simulation data with internal teams and external stakeholders, including industry panels and customer reviews.

Document design features, test plans, and results, and consult on electrical characterization and post-silicon analysis for product enhancements.

Analyze customer silicon data to identify design improvement opportunities and propose solutions for post-silicon updates.

What you need

MTech/MS with 7+ years or BTech/BS with 8+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).

Proven expertise with FinFET technologies and CMOS tape-outs.

Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.

Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).

Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.

Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).

Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.

Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.

Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).

Excellent communication and documentation skills.

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What you'll do

You are an accomplished analog and mixed-signal design engineer, passionate about pushing the boundaries of high-speed interface technology. With a strong foundation in Electrical, Electronics, or VLSI Engineering, you have hands-on expertise in custom analog circuit design, particularly in the nanometer CMOS domain.

• Designing and developing high-speed analog and mixed-signal (AMS) circuit macros, including analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, regulators, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers/deserializers, VCOs, phase interpolators, bandgap references, CDR circuits, and injection-locked loops for High-Speed PHY IP in planar and FinFET CMOS technologies.

What you need

• Bachelor’s degree (BE) plus 3+ years or Master’s degree (MTech) plus 2+ years of relevant experience in mixed-signal analog/custom circuit design, preferably in Electrical/Electronics/VLSI Engineering.

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What you'll do

Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment.

• Collaborate with cross-functional teams to ensure successful project execution.

• Create and review layout documents to ensure they meet quality standards and are delivered on time.

What you need

Bachelor's or Master's degree in Electrical Engineering or a related field.

• Minimum 9+ years of experience in Analog and Mixed Signal Circuit Layout.

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