We are seeking an experienced Application Engineer to join our team in Bengaluru. As a Staff Engineer, you will be responsible for developing and validating DRC, LVS, and Fill runsets for the Synopsys IC Validator tool. You will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.
\nYour responsibilities will include:
\nYou will accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. You will ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. You will drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. You will enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. You will contribute to the development of next-generation verification methodologies and best practices within Synopsys. You will strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.
\nTo be successful in this role, you will need:
\nYou will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.
\nRewards and benefits include a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nAs a Sr. Manager of R&D Engineering, you will lead a team of engineers in developing cutting-edge CMOS embedded memory technologies. You will be responsible for designing architecture and circuit implementation for ultra-high-speed, ultra-low-power, or high-density designs. You will also perform schematic entry, circuit simulation, layout planning, and supervision, as well as verify and validate designs to ensure high quality and performance.
\nThe ideal candidate will have a strong background in memory compiler development, with a minimum of 8-10 years of experience in CMOS memory design, circuit simulation, and memory layout design. You will also have experience with layout parasitic extraction and verification tools, as well as programming skills in C-Shell, Perl, C++, or JavaScript.
\nAs a leader, you will be responsible for mentoring and guiding a team of engineers, enhancing workflows and methodologies, and driving project success. You will also be expected to communicate effectively with cross-functional teams, including CAD and Frontend engineers, to automate memory compilers and generate EDA models.
\nAt Synopsys, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nAs a Sr Engineer, you will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. You will automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
\nResponsibilities:
\nImpact:
\nRequirements:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process
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\nJob Description:
\nAs an intern in the Analog Design Engineering team, you will design, verify, and validate high-performance, high-speed analog circuits, focusing on next-generation Phase Lock Loops (PLLs) and related blocks for world-leading SOCs in advanced CMOS technologies. You will participate in the design of Delay Locked Loops (DLL), phase mixers, and custom digital blocks used in SERDES interfaces. You will contribute to test bench creation, specification generation, analog circuit design, and layout optimization. You will assist with documentation, design debugging, and silicon evaluation to ensure robust and reliable circuit performance. You will engage with cross-functional teams, sharing ideas and collaborating to solve complex engineering challenges.
\nRequirements:
\nProgram Facts:
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\nThey work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nThese engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nAt Synopsys, we drive the innovations that shape the way we live and connect.
\nOur technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.
\nWe lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nJoin us to transform the future through continuous technological innovation.
\nYou are a visionary and detail-oriented principal engineer, passionate about pushing the boundaries of analog circuit design in high-speed interfaces.
\nWith a deep technical foundation and proven leadership skills, you thrive in collaborative environments and are eager to mentor the next generation of engineers.
\nYour expertise in SerDes and analog macros enables you to dissect complex architectural requirements and translate them into robust, scalable designs.
\nYou are adept at balancing power, area, and performance trade-offs, and you proactively seek innovative solutions to technical challenges.
\nYour experience spans both the theoretical and practical aspects of circuit design,from transistor-level fundamentals to silicon-proven implementations.
\nYou champion rigorous verification methodologies and leverage advanced simulation tools to ensure the highest quality outcomes.
\nAs a communicator, you clearly articulate your ideas to peers, customers, and junior team members, fostering a culture of learning and excellence.
\nYou are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you approach every project with a commitment to reliability, efficiency, and continuous improvement.
\nYour adaptability and curiosity make you a valuable contributor to cross-functional teams, and you are excited to make a lasting impact at Synopsys.
\nOwn the architecture, design, and implementation of analog macro-level circuits for SerDes IP.
\nTrack and review the technical progress of sub-block owners, ensuring alignment with project goals.
\nInterpret SerDes standards and architecture documents to develop detailed analog specifications.
\nIdentify and refine circuit implementations, optimizing for power, area, and performance targets.
\nPropose and execute design and verification strategies using advanced simulator features for robust outcomes.
\nOversee physical layout to minimize parasitics, device stress, and process variation impacts.
\nCollaborate closely with digital RTL engineers on calibration, adaptation, and control algorithms for analog circuits.
\nPresent simulation data and technical insights for peer and customer reviews.
\nMentor and review the progress of junior engineers, fostering growth and technical excellence.
\nDocument design features, methodologies, and test plans for internal and customer use.
\nConsult on electrical characterization and testing of circuits within the SerDes IP product portfolio.
\nDrive innovation and quality in Synopsys’ industry-leading SerDes IP solutions.
\nElevate the performance and reliability of analog designs, enabling next-generation connectivity standards.
\nContribute to the success of global customers by delivering robust, silicon-proven analog macros.
\nEnhance cross-functional collaboration across design, layout, and digital teams.
\nMentor and develop junior engineers, strengthening Synopsys’ talent pipeline.
\nInfluence the direction of advanced analog design methodologies and verification strategies.
\nProvide technical leadership in customer engagements and peer reviews.
\nSupport continuous improvement in design processes and documentation practices.
\nPhD with 7+ years, or MSc with 10+ years of SerDes/high-speed analog design experience.
\nExpertise in transistor-level circuit design and strong CMOS design fundamentals.
\nSilicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.
\nLeadership experience in guiding small teams through macro-level design projects.
\nIn-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
\nAdvanced skills in optimizing FinFET CMOS layouts to minimize parasitics and local device mismatches.
\nAwareness of ESD and reliability issues, including circuit techniques and layout strategies.
\nProficiency with EDA tools for schematic entry, physical layout, and design verification.
\nExperience with SPICE simulators for detailed circuit analysis.
\nFamiliarity with analog behavioral modeling and simulation control using Verilog-A.
\nProgramming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.
\nAnalytical thinker with exceptional problem-solving skills.
\nCollaborative leader and effective communicator.
\nDetail-oriented and methodical in approach.
\nAdaptable and open to learning new technologies.
\nMentor and role model for junior engineers.
\nSelf-motivated and proactive in driving project outcomes.
\nCommitted to excellence, reliability, and innovation.
\nYou will join a dynamic and multidisciplinary team of analog, digital, and mixed-signal engineers dedicated to developing industry-leading SerDes IP solutions.
\nThe team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products.
\nCollaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
\nOur total rewards include both monetary and non-monetary offerings.
\nYour recruiter will provide more details about the salary range and benefits during the hiring process.
\nSynopsys Canada ULC values the diversity of our workforce.
\nWe are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.
\nShould you require an accommodation, please contact hr-help-canada@synopsys.com.
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\nOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nYou will be a part of a fast-growing analog and mixed-signal R&D team, dedicated to developing high-speed analog integrated circuits in the most advanced FinFET/GAA process nodes. You'll interact with a global, dynamic, multi-cultural, and cross-functional design team, collaborating with experts in various fields to create innovative solutions for high-speed communications.
\nAs a Staff Engineer, you will be responsible for:
\nDeveloping and/or validating analog circuits considering electrical specifications and reliability constraints.\nDocumenting simulation results and analyzing performance.\nEvaluating the impact of parasitic effects related to layout implementations and working with the layout team to minimize such effects, improving performance, power, and area.\nDefining and planning analog design activities for high-speed SerDes products.\nCollaborating with a global team of engineers to integrate and verify design solutions.\nContinuously learning and applying the latest advancements in FinFET/GAA process nodes to enhance design efficiency.
\nYou will contribute to the development of high-speed SerDes products that enable high-performance chip-to-chip communications. You will enhance the performance, power efficiency, and reliability of analog integrated circuits in advanced CMOS technologies. You will support the integration of more capabilities into System-on-Chip (SoC) designs, accelerating time-to-market for innovative products.
\nYou will be a part of a dynamic, multicultural, and cross-functional design team, collaborating with experts in various fields to create innovative solutions for high-speed communications.
\nThe ideal candidate will have a good understanding of CMOS technologies and analog circuit design principles. They will have strong analysis, problem-solving, and organizational skills. They will have experience in analog and mixed-signal block design, with a focus on high-speed SERDES. They will be proficient in documenting and analyzing simulation results. They will be familiar with IC design packages and UNIX operating systems.
\nYou will be a collaborative team player who thrives in a global, multicultural environment. You will be an effective communicator with strong written and verbal skills in English. You will be a proactive and self-motivated individual with a passion for innovation and continuous learning. You will be an analytical thinker with the ability to tackle complex design challenges and find creative solutions. You will be a detail-oriented engineer who values precision and accuracy in their work.
\nYou will be rewarded with a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nInclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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\nYou are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience,primarily in Physical Verification (PV),you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.
\nYou are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements. As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment. Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions. You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.
\nDeveloping and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.\nCollaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.\nAutomating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.\nTroubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.\nInterfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.\nMentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.\nStaying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.
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\nThese engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nWe are hiring a Staff Engineer to lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.
\nAs a Staff Engineer, you will be responsible for leading the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies. You will work on hands-on execution of layout development, ensuring precision and adherence to industry standards.
\nYou will also mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.
\nEstimating project efforts, planning schedules, and executing projects in cross-functional settings will be another key responsibility.
\nCollaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks will also be a part of your role.
\nManaging the release process, ensuring timely delivery and consistent quality of layout deliverables will be your additional responsibility.
\nKey Responsibilities:
\nLead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.
\nHands-on execution of layout development, ensuring precision and adherence to industry standards.
\nMentor and support junior engineers, fostering technical growth and knowledge sharing within the team.
\nEstimating project efforts, planning schedules, and executing projects in cross-functional settings.
\nCollaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.
\nManaging the release process, ensuring timely delivery and consistent quality of layout deliverables.
\nRequirements:
\nBTech/MTech degree in Electrical Engineering, Electronics, or related field.
\n5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).
\nExpertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.
\nStrong understanding of floorplan techniques and deep submicron effects.
\nProven ability to lead projects and deliver best product quality within tight timelines.
\nPreferred Qualifications:
\nCollaborative and team-oriented, with a commitment to inclusion and diversity.
\nDetail-oriented, with strong problem-solving and analytical skills.
\nEffective communicator, both written and verbal, with excellent interpersonal abilities.
\nAdaptable and eager to learn, embracing new technologies and methodologies.
\nEmpathetic mentor, fostering accountability, ownership, and technical growth in others.
\nBenefits:
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
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\nIf you are a passionate engineer with a deep understanding of optics and photonics, eager to solve challenging engineering problems and make a significant impact in the industry, we encourage you to apply for this exciting opportunity.
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\nYou Are:
\nA Staff-level analog/MS engineer who owns complex designs end-to-end, influences architecture, and mentors others. You balance performance, reliability, and schedule in advanced CMOS and communicate clearly across teams.
\nIf you are excited by the prospect of shaping high-speed connectivity in AI, cloud, automotive, and beyond - and you seek to empower some of the world's most advanced systems - this role is your opportunity to make a meaningful impact.
\nWhat You'll Be Doing:
\nWhat You'll Need:
\nThe Team You'll Be A Part Of:
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\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nWhat You’ll Need:
\nB.Tech/BE/M.Tech/MS in Electronics Engineering.\n8+ years of experience in Analog Design for High-Speed SerDes applications.\n3-5 years of experience in a management or supervisory role.\nIn-depth familiarity with transistor level circuit design and sound CMOS design fundamentals.\nDetailed design experience with SerDes sub-circuits such as receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers,voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, and DAC, DSP, Signal Integrity\nFamiliarity with both analog and digital circuits and issues related to interfacing and timing between them.\nAware of ESD issues (i.e. circuit techniques, layout).\nFamiliarity with custom digital design (i.e. highspeed logic paths).\nKnowledge of design for reliability (i.e. EM, IR, aging, etc.).\nKnowledge of layout effects (i.e. matching, reliability, proximity effects, etc.).\nGood communication and documentation skills.
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\nDriving the development of high-speed SerDes IP that meets industry standards and customer requirements.\nFostering innovation and excellence within the analog design team.\nEnsuring the delivery of high-quality, reliable analog integrated circuits.\nContributing to the advancement of Synopsys' technology portfolio in the analog and mixed-signal domains.\nEnhancing the performance and efficiency of our high-speed communication products.\nSupporting the growth and development of team members through effective leadership and mentorship.
\nWho You Are:
\nYou are a proactive leader with a strong technical background in analog design. You possess excellent problem-solving skills and the ability to make sound decisions under pressure. Your collaborative nature allows you to work effectively with cross-functional teams. You are detail-oriented and have a keen eye for quality. Your passion for continuous learning and improvement drives you to stay updated with the latest industry trends and technologies. You are committed to fostering a positive and inclusive team culture, encouraging innovation and excellence.
\nThe Team You’ll Be A Part Of:
\nYou will be part of a fast-growing analog and mixed-signal R&D team developing high-speed analog integrated circuits in the latest FinFET process nodes. The team is composed of talented analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nWe are seeking an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology.
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\nDeveloping and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
\nCollaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.
\nAutomating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
\nTroubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.
\nInterfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.
\nMentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.
\nStaying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.
\nAccelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses.
\nEnsure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market.
\nDrive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps.
\nEnhance customer satisfaction by providing timely and expert solutions to complex verification challenges.
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\nStrengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.
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\n5-8 years of hands-on experience in the Physical Verification (PV) domain.
\nAdvanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
\nStrong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
\nDeep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
\nExperience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
\nExposure to competitive EDA tools and awareness of their strengths and limitations.
\nAn analytical thinker with strong problem-solving abilities and meticulous attention to detail.
\nA collaborative team player who fosters knowledge sharing and mentorship.
\nEffective communicator, capable of translating technical concepts to diverse audiences.
\nAdaptable and proactive, with a passion for continuous learning and innovation.
\nCustomer-focused, with a commitment to delivering high-quality solutions on time.
\nSelf-driven, organized, and able to manage multiple priorities in a fast-paced environment.
\nJoin a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design.
\nWork closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
\nOur total rewards include both monetary and non-monetary offerings.
\nYour recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work.
\nSynopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
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\nJob Description
\nCategory
\nEngineering
\nHire Type
\nEmployee
\nJob ID
\n15231
\nRemote Eligible
\nNo
\nDate Posted
\n02/15/2026
\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
\nYou Are:
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nJoin our High-Performance Computing (HPC) Enterprise analog/mixed-signal Serdes team involved in cutting-edge High Speed PHYSICAL Interface Development.
\nYou will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
\n\\\\ Benefits vary by country and region - check with your recruiter to confirm
\nGet an idea of what your daily routine around the office can be like
\n\\ Explore Noida
\nView Map
\n---
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\nYour contributions will drive innovation in SRAM IP design, maintaining Synopsys’s leadership in memory technology. You will enhance product performance and reliability for global semiconductor customers. You will support the delivery of best-in-class SRAM compilers used in high-performance silicon chips. You will strengthen quality assurance processes, ensuring robust and scalable designs. You will accelerate time-to-market for new memory IP solutions through efficient verification and debug activities. You will contribute to the development of advanced memory architectures, impacting next-generation electronic devices.
\nTo be successful in this role, you will need a Master’s degree in Electrical/Electronic Engineering or a related field. You will have 3–7+ years of hands-on experience in SRAM circuit design. You will have prior understanding of CMOS-based block level circuit design and SRAM architectures. You will have experience with SP/2P/ROM variety design and SRAM bitcell analysis. You will be proficient in digital circuit design and VLSI process concepts. You will have familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell. You will have experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR. Post-silicon debug experience is a plus.
\nYou will be an analytical thinker with strong problem-solving skills. You will be curious and eager to learn new technologies and concepts. You will be detail-oriented and committed to delivering high-quality results. You will be a collaborative team player with effective communication skills. You will be adaptable and able to manage multiple tasks in a fast-paced environment. You will be self-motivated and resourceful in overcoming technical challenges.
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\nJob Description
\nCategory
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\nHire Type
\nEmployee
\nJob ID
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\nRemote Eligible
\nNo
\nDate Posted
\n02/23/2026
\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
\nYou Are:
\nYou are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ & PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.
\nYou excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.
\nBeyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou’ll join a world-class analog and mixed-signal R&D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nWhat is it like to be an Analog Design Engineer at Synopsys?
\nArman Shahmuradyan
\nAnalog Design, Manager
\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and patern
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\nWhat you'll do
\nWhat you need
\nXML job scraping automation by YubHub
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\nWhat you'll do
\nAs a Staff Engineer, you will be responsible for designing and developing advanced embedded memories (SRAM, ROM, Register File).
\nWhat you need
\nXML job scraping automation by YubHub
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\nWhat you'll do
\nReview SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.
\nInvestigate and architect circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.
\nCollaborate with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.
\nOversee and guide the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.
\nPresent and review simulation data with internal teams and external stakeholders, including industry panels and customer reviews.
\nDocument design features, test plans, and results, and consult on electrical characterization and post-silicon analysis for product enhancements.
\nAnalyze customer silicon data to identify design improvement opportunities and propose solutions for post-silicon updates.
\nWhat you need
\nMTech/MS with 7+ years or BTech/BS with 8+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).
\nProven expertise with FinFET technologies and CMOS tape-outs.
\nDeep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.
\nExtensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).
\nSkilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.
\nFamiliarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).
\nProficient with schematic entry, physical layout, design verification tools, and SPICE simulators.
\nExperience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.
\nUnderstanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).
\nExcellent communication and documentation skills.
\nXML job scraping automation by YubHub
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\nWhat you'll do
\nYou are an accomplished analog and mixed-signal design engineer, passionate about pushing the boundaries of high-speed interface technology. With a strong foundation in Electrical, Electronics, or VLSI Engineering, you have hands-on expertise in custom analog circuit design, particularly in the nanometer CMOS domain.
\nWhat you need
\nXML job scraping automation by YubHub
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\nWhat you'll do
\nPlan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment.
\nWhat you need
\nBachelor's or Master's degree in Electrical Engineering or a related field.
\nXML job scraping automation by YubHub
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