We are seeking an experienced Application Engineer to join our team in Bengaluru. As a Staff Engineer, you will be responsible for developing and validating DRC, LVS, and Fill runsets for the Synopsys IC Validator tool. You will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.
\nYour responsibilities will include:
\nYou will accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. You will ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. You will drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. You will enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. You will contribute to the development of next-generation verification methodologies and best practices within Synopsys. You will strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.
\nTo be successful in this role, you will need:
\nYou will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.
\nRewards and benefits include a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nAs a Sr Engineer, you will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. You will automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
\nResponsibilities:
\nImpact:
\nRequirements:
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\nThe Team You’ll Be A Part Of:
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\nRewards and Benefits:
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\nYou are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience,primarily in Physical Verification (PV),you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.
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\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
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\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
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\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
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\nAt Synopsys, Apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide,and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests.
\nResponsibilities: Support layout development of analog and mixed-signal CMOS layouts. Collaborate with layout engineers to understand schematics and implement corresponding layouts. Assist in resolving layout issues and participate in physical verification flows. Learn and follow standard layout methodologies, best practices, and tool flows. Coordinate with team members to ensure timely completion of layout tasks.
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\nKey Program Facts: Program Length: 12 months apprenticeship program. Location: Bengaluru, India. Working Model: In-office. Full-Time/Part-Time: Full-time. Start Date: March / April 2026.
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\nThey work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nThese engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nWe are seeking an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology.
\nWith 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes.
\nYou possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus.
\nYour proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.
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\nYou are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.
\nDeveloping and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
\nCollaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.
\nAutomating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
\nTroubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.
\nInterfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.
\nMentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.
\nStaying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.
\nAccelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses.
\nEnsure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market.
\nDrive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps.
\nEnhance customer satisfaction by providing timely and expert solutions to complex verification challenges.
\nContribute to the development of next-generation verification methodologies and best practices within Synopsys.
\nStrengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.
\nB.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.
\n5-8 years of hands-on experience in the Physical Verification (PV) domain.
\nAdvanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
\nStrong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
\nDeep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
\nExperience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
\nExposure to competitive EDA tools and awareness of their strengths and limitations.
\nAn analytical thinker with strong problem-solving abilities and meticulous attention to detail.
\nA collaborative team player who fosters knowledge sharing and mentorship.
\nEffective communicator, capable of translating technical concepts to diverse audiences.
\nAdaptable and proactive, with a passion for continuous learning and innovation.
\nCustomer-focused, with a commitment to delivering high-quality solutions on time.
\nSelf-driven, organized, and able to manage multiple priorities in a fast-paced environment.
\nJoin a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design.
\nWork closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
\nOur total rewards include both monetary and non-monetary offerings.
\nYour recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work.
\nSynopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
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\nYou Are:\nYou are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.
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\nRequirements:\nB.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.\n5-8 years of hands-on experience in the Physical Verification (PV) domain.\nAdvanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.\nStrong scripting skills in Perl, Tcl, and Python for automation and rule deck development.\nDeep understanding of CMOS layout, ASIC design flows, and foundry process requirements.\nExperience in writing and debugging DRC, LVS, ERC, and DFM rule decks.\nExposure to competitive EDA tools and awareness of their strengths and limitations.
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\nThe Team You’ll Be A Part Of:\nYou will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.
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\nWhat you need
\nXML job scraping automation by YubHub
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