These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a UCIe Analog Design Senior Engineer at Synopsys, you will design circuit for Analog IPs like High Speed IOs, LCDL, Bandgap, High Speed macros for high speed PHY, Clock trees, Calibration circuits...

You will analyze and verify to make sure design meet all requirements of functionality, performance, area and reliability.

You will work closely with layout engineers to make sure layout quality. Perform post layout verifications.

You will perform design characterizations, functionality checks, EMIR analysis, Co-simulations for Logic-Analog full chip operations.

You will design analysis and solve problems of noise, margin, signal integrity, power integrity.

You will complete all design quality checks and data quality checks

You will do design reviews across global team

You will work with digital/system engineer to integrate analog designs into mixed signal system. Perform mixed signal verification which combining both analog and digital blocks.

You will train for fresh engineers and interns

The ideal candidate will have a BS/MS in Electronics Engineering, Electromechanics, Telecommunications.

They should have 0-3 years of experience in Analog, Mixed Signal, Memory or Custom logic Circuit design.

They should have solid knowledge of CMOS Analog design knowledge and techniques

They should have solid skill with circuit design tools: SNSP Custom Designer, Cadence Virtuoso

They should have solid understanding circuit simulation tools: Hspice or Spectre or Custom Sim...

They should have good understanding of layout effects on circuit performance.

They should have experienced with writing design review presentations and circuit verification reports

They should have good English communication both verbally and in writing

They should be a great team player, willing to support others.

They should be highly responsible, result oriented.

They should be self-motivated and highly enthusiasm in technology and solving problems

Leadership skill and experience is a plus

Familiar with high speed analog designs, IO designs, PLL/DLL is a plus

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What you'll do

• Develop accurate timing models for macros used in multi-die designs.
• Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements.

What you need

• BS/MS in Electronics, Electromechanics, or Telecommunications.
• 5-8 years in analog/mixed signal or custom logic design.

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