{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/clock-domain-crossing"},"x-facet":{"type":"skill","slug":"clock-domain-crossing","display":"Clock Domain Crossing","count":3},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7026ea72-dd8"},"title":"RTL Design, Sr Engineer","description":"<p>We are seeking a skilled RTL Design Engineer to join our team in Hanoi/Ho Chi Minh City/Da Nang. As a member of our team, you will be responsible for developing specifications and RTL for High Bandwidth Interface PHY IP. You will collaborate with Verification teams to ensure design accuracy and coordinate logic implementation phases across teams. You will also apply scripting skills for design automation and participate in onboarding in Da Nang and transitioning to Hanoi or Ho Chi Minh City.</p>\n<p>The successful candidate will have a BS/MS/PhD in Electronics Engineering or Telecommunications and 2+ years of experience in RTL design for ASIC or PHY IP. You will have experience with VCS, Verdi, Spyglass, Perl/TCL/Python and knowledge of clock domain crossing, APB, JTAG. Good English communication skills are essential.</p>\n<p>As a member of our team, you will advance industry-leading high bandwidth interface IP, ensure robust design and verification processes, drive innovation in RTL design and workflows, and enhance productivity through automation.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7026ea72-dd8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/rtl-design-sr-engineer-in-hanoi-hcmc-da-nang/44408/92454718896","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design","ASIC design","PHY IP","VCS","Verdi","Spyglass","Perl","TCL","Python","clock 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Description</strong></p>\n<p>We are seeking an experienced RTL design engineer with a strong background in electronics or telecommunications.</p>\n<p>With over five years in ASIC or PHY IP development, you’re passionate about solving technical challenges, collaborating with cross-functional teams, and mentoring others.</p>\n<p>Your communication skills and attention to detail ensure projects run smoothly from specification to silicon debug.</p>\n<p>You thrive in fast-paced environments and are eager to contribute to groundbreaking technology.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Develop RTL specifications and architectures for High Bandwidth Interface PHY IP.</li>\n</ul>\n<ul>\n<li>Define synthesis constraints and resolve STA and gate-level simulation issues.</li>\n</ul>\n<ul>\n<li>Collaborate with verification, controller, and lab teams for design and debugging.</li>\n</ul>\n<ul>\n<li>Support RTL to GDS flow during logic implementation.</li>\n</ul>\n<ul>\n<li>Lead projects and train junior engineers.</li>\n</ul>\n<ul>\n<li>Work with customers to resolve technical RTL issues.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver robust RTL designs for advanced silicon solutions.</li>\n</ul>\n<ul>\n<li>Drive successful project completion and tape-outs.</li>\n</ul>\n<ul>\n<li>Enhance design quality and verification efficiency.</li>\n</ul>\n<ul>\n<li>Support customer success and strengthen Synopsys’ reputation.</li>\n</ul>\n<ul>\n<li>Mentor and grow engineering talent within the team.</li>\n</ul>\n<ul>\n<li>Contribute to digital flow improvements and innovation.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>BS/MS/PhD in Electronics Engineering or Telecommunications.</li>\n</ul>\n<ul>\n<li>5+ years of RTL design experience for ASIC or PHY IP.</li>\n</ul>\n<ul>\n<li>Expertise in VCS, Verdi, Spyglass, and scripting (Perl, TCL, Python).</li>\n</ul>\n<ul>\n<li>Knowledge of clock domain crossing, APB, JTAG protocols.</li>\n</ul>\n<ul>\n<li>Strong English communication skills.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Responsible, result-oriented, and self-motivated.</li>\n</ul>\n<ul>\n<li>Collaborative and proactive problem solver.</li>\n</ul>\n<ul>\n<li>Effective communicator and mentor.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>Join a collaborative engineering team delivering innovative PHY IP solutions.</p>\n<p>Work alongside experts in Ho Chi Minh City, Da Nang, or Hanoi, and contribute to Synopsys’ global leadership in semiconductor technology.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits.</p>\n<p>Your recruiter will provide more details about salary and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a 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With a strong theoretical and practical background in high-speed data recovery circuits, you are eager to contribute your expertise to cutting-edge mixed-signal designs.</p>\n<p>You have a proven track record in digital design and verification, and you are comfortable working across ASIC, FPGA, and firmware domains. Your experience enables you to interpret and review digital and analog specifications, create robust analog models, and write modular, constrained-random testbenches in Verilog and SystemVerilog.</p>\n<p>You are adept at performing functional, assertion, and code coverage, and you have a keen eye for failure analysis and testplan management. Your organisational skills ensure that projects move forward efficiently, and your communication abilities allow you to interface effectively with multidisciplinary teams and customer support groups.</p>\n<p>You value diversity, inclusivity, and continuous learning, seeking out opportunities to grow and mentor others. As someone who is motivated by innovation, you are excited to work with an expert team and help deliver high-end mixed-signal designs that power the next generation of smart technology.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li>Designing and verifying ASIC, FPGA, and firmware for high-speed mixed-signal circuits.</li>\n</ul>\n<ul>\n<li>Reviewing digital and analog specifications to ensure alignment with project goals.</li>\n</ul>\n<ul>\n<li>Creating analog models based on schematics and functional requirements.</li>\n</ul>\n<ul>\n<li>Developing modular, constrained-random testbenches in Verilog and SystemVerilog for robust verification.</li>\n</ul>\n<ul>\n<li>Performing functional, assertion, and code coverage, analysing results to identify areas for improvement.</li>\n</ul>\n<ul>\n<li>Developing, managing, and tracking comprehensive testplans to ensure thorough verification.</li>\n</ul>\n<ul>\n<li>Reviewing and analysing failure cases to drive corrective actions and enhance product reliability.</li>\n</ul>\n<ul>\n<li>Running gate-level simulations to validate design integrity and performance.</li>\n</ul>\n<ul>\n<li>Collaborating with cross-functional design groups and customer support teams to resolve technical challenges.</li>\n</ul>\n<p><strong>Impact:</strong></p>\n<ul>\n<li>Advancing the development of high-performance mixed-signal designs that enable next-generation applications.</li>\n</ul>\n<ul>\n<li>Ensuring functional and performance integrity of silicon IP products through rigorous verification.</li>\n</ul>\n<ul>\n<li>Accelerating time-to-market for differentiated products by reducing risk and increasing design confidence.</li>\n</ul>\n<ul>\n<li>Contributing to the world&#39;s broadest portfolio of silicon IP, supporting innovation in AI, IoT, 5G, and more.</li>\n</ul>\n<ul>\n<li>Enhancing reliability and quality of products that power smart devices and autonomous systems.</li>\n</ul>\n<ul>\n<li>Supporting Synopsys&#39; reputation as a leader in chip design and software security by delivering excellence.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>BSEE with 2 years of digital design and verification experience, or MSEE with 0 years of digital design and verification industry experience.</li>\n</ul>\n<ul>\n<li>Expertise in ASIC design, synthesis, and clock domain crossing (CDC).</li>\n</ul>\n<ul>\n<li>Hands-on experience writing complex testcases in Verilog and SystemVerilog.</li>\n</ul>\n<ul>\n<li>Familiarity with code quality metrics and best practices in verification methodologies.</li>\n</ul>\n<ul>\n<li>Ability to create system-level specifications for digital and analog domains.</li>\n</ul>\n<ul>\n<li>Strong knowledge of high-speed digital and mixed-signal design principles.</li>\n</ul>\n<ul>\n<li>Experience with asynchronous clock crossings and DFT (Design For Test) methodologies.</li>\n</ul>\n<p><strong>Team:</strong></p>\n<p>Join a highly experienced mixed-signal design team, dedicated to delivering high-end mixed-signal designs from specification development through functional and performance testing. You&#39;ll be working alongside expert digital and mixed-signal engineers, collaborating across design, verification, and customer support to push the boundaries of innovation in silicon IP and SoC integration.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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