These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a UCIe Analog Design Senior Engineer at Synopsys, you will design circuit for Analog IPs like High Speed IOs, LCDL, Bandgap, High Speed macros for high speed PHY, Clock trees, Calibration circuits...

You will analyze and verify to make sure design meet all requirements of functionality, performance, area and reliability.

You will work closely with layout engineers to make sure layout quality. Perform post layout verifications.

You will perform design characterizations, functionality checks, EMIR analysis, Co-simulations for Logic-Analog full chip operations.

You will design analysis and solve problems of noise, margin, signal integrity, power integrity.

You will complete all design quality checks and data quality checks

You will do design reviews across global team

You will work with digital/system engineer to integrate analog designs into mixed signal system. Perform mixed signal verification which combining both analog and digital blocks.

You will train for fresh engineers and interns

The ideal candidate will have a BS/MS in Electronics Engineering, Electromechanics, Telecommunications.

They should have 0-3 years of experience in Analog, Mixed Signal, Memory or Custom logic Circuit design.

They should have solid knowledge of CMOS Analog design knowledge and techniques

They should have solid skill with circuit design tools: SNSP Custom Designer, Cadence Virtuoso

They should have solid understanding circuit simulation tools: Hspice or Spectre or Custom Sim...

They should have good understanding of layout effects on circuit performance.

They should have experienced with writing design review presentations and circuit verification reports

They should have good English communication both verbally and in writing

They should be a great team player, willing to support others.

They should be highly responsible, result oriented.

They should be self-motivated and highly enthusiasm in technology and solving problems

Leadership skill and experience is a plus

Familiar with high speed analog designs, IO designs, PLL/DLL is a plus

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Responsibilities:

• Design, prototype, build and test high-voltage battery management electronics for Fuse Energy’s stationary storage and grid-connected systems
• Own end-to-end PCBA development, including requirements definition, schematic capture, PCB layout, design reviews and design for manufacturability
• Develop automated validation setups and test firmware/software to ensure comprehensive functional, performance and safety coverage of BMS designs
• Support the transition of designs from prototype to production, including supplier engagement, bring-up and production test strategy
• Collaborate with firmware and software engineers to define hardware–software interfaces, diagnostics and safety mechanisms
• Work closely with mechanical and systems engineers to ensure electrical designs are optimised for thermal performance, isolation and environmental constraints
• Perform detailed failure analysis and root-cause investigations on PCBAs and systems in both lab and field environments
• Evaluate, select and integrate battery monitoring ICs, microcontrollers, isolation components and communication interfaces suitable for high-voltage applications
• Continuously improve designs to optimise reliability, component availability and BOM cost as systems scale

Requirements:

• Bachelor’s degree in Electrical or Electronic Engineering or equivalent practical experience
• At least 5 years of hands-on industry experience in analog and digital electronics design
• Strong fundamentals in circuit analysis, simulation and design trade-off evaluation
• Proven experience designing and debugging complex PCBAs with excellent failure analysis and troubleshooting skills
• Solid proficiency in Python for test automation, validation and data analysis
• Experience in one or more of the following domains: battery management systems, power electronics, high-voltage systems, microcontrollers or high-speed digital interfaces
• Familiarity with communication interfaces commonly used in BMS and energy systems (e.g. CAN, RS485, Ethernet, SPI, I²C)
• Experience with Altium Designer and circuit simulation tools such as LTSpice
• Exposure to mechanical CAD tools (e.g. Fusion 360, SolidWorks or similar), rapid prototyping and close collaboration with mechanical design

Benefits:

• Competitive salary and an equity sign-on bonus
• Biannual bonus scheme
• Fully expensed tech to match your needs
• Paid annual leave
• Breakfast and dinner allowance for office based employees

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What you'll do

• Responsible for modeling(IBIS, AMI,CMM, CPM, CTM), simulating, analyzing signal and power integrity (SIPI), troubleshooting, and reviewing interfaces interconnect.
• Performs, verifies, and documents interface SIPI analysis outcome as part of global chip design team.
• Carry out experiments to validate modeling and methodologies.
• Develop and document signal and power integrity requirements and flows for internal and external customer use.

What you need

• Possesses excellent communication skills, both verbal and written.
• Familiarity with both Windows and Linux operating system is required.
• An understanding of basic circuit and transmission line theory is essential, as is familiarity with and a working knowledge of concurrent time and frequency-domain methods of analysis and characterization.
• Knowledge on interface such as UCIE is a plus, though DDR, HBM, PCIe (e.g. gen 6/5), Ethernet, SATA, for example, can be leveraged.
• Some experience in programming languages such as Python, TCL and Matlab is desired.
• A working knowledge of circuit simulation tools such as Synopsys HSPICE is required. Experience with Redhawk, Totem, Ansys AEDT, Keysight ADS, etc. is a plus.
• Practical experience with package and pcb design 3D electro-magnetic field solvers such as Ansys SiWave/HFSS, with proven ability to create models of usable bandwidth up-to 20GHz is preferred.
• Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills.
• Bachelor's or Master's degree in Electrical or Electronics Engineering, with a minimum of 6 years of relevant experience in supporting interface IP product development (preferably DDR), system integration and Signal and Power verifications flow/methodologies.

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What you'll do

You will lead the NVM TestChip and IP design flow across multiple technologies and foundries, ensuring robust and scalable solutions for diverse applications.

• Architecting, designing, and verifying CMOS-based non-volatile memory IP modules, from concept to production tapeout.
• Collaborating with product engineers to perform silicon verification, in-depth testing, and debugging to validate IP performance on silicon.
• Conducting post-layout extraction, simulation, and comprehensive testing in conjunction with silicon validation teams.

What you need

• 5–12+ years of industry experience in circuit design, with a strong emphasis on analog circuit design and analysis; memory design experience is a significant plus.
• Deep understanding of layout considerations for advanced nodes, including parasitic effects, matching techniques, and signal integrity.
• Expertise in electrical problem-solving, including root cause analysis of circuit failures and development of effective solutions.
• Hands-on experience with TestChip tapeout flows, silicon debugging (FIB, micro-probing, post-layout RC extraction), and statistical design methodologies (e.g., Monte-Carlo analysis).
• Strong transistor-level analog design skills, including sense-amplifier, charge pump, high voltage regulator, and bandgap reference circuit design.
• Proficiency with circuit simulation tools (HSIM, HSPICE, etc.) and custom schematic/layout editors (e.g., Custom Compiler).
• Experience with low power design, power management circuitry, and FinFET design is a plus.

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