Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.

Responsibilities:

• Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.
• Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.

Requirements:

• Minimum 5+ years of experience in IP/ASIC/SOC design implementation.
• Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.
• Good communication skills while interacting with internal teams and customers.

Preferred Experience:

• Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.
• Experience in DesignWare Core IPs or PHYs.
• Experience in TCL, Perl, Python, or other shell scripting.

Benefits:

• Competitive salary and benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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You are a dynamic engineer with working experience in RTL implementation, DFT, verification, flow automation and understanding of 3DIC solutions and UCIe protocols. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them at our premier customer base. Your technical excellence and analytical skills, coupled with strong communication and interpersonal skills, make you an asset to any team.

Key responsibilities include:

• Working closely with a world-class R&D team, you’ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) and 3DIC technologies.

• Working closely with customers, you will bring detailed requirements into the factory to enable R&D for strong, robust, and successful product development.

• Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.

• Driving the deployment and smooth execution of SLM solutions into customers’ projects.

• Enabling customers to realize the value of silicon health monitoring in the context of 3DIC systems throughout the lifecycle of silicon bring-up, validation, through in-field operations.

The impact you will have includes enhancing Synopsys’ Silicon Lifecycle Management (SLM) and 3DIC solutions’ IP portfolio and end-to-end solution especially in the growing field of multi-die (3DIC) domain, driving the adoption of Synopsys’ SLM and 3DIC solutions at premier customer base worldwide, and influencing the development of next-generation SLM IPs and solutions.

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You are a dynamic engineer with working experience in RTL implementation, DFT/BIST, verification, flow automation, and understanding of hierarchical SoC architectures and IEEE1149/1500 and 1687 standards and pattern porting. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them in our premier customer base.

What You'll Be Doing:

• Working closely with a world-class R&D team, you'll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) built over a robust DFT framework.
• Working closely with customers, you will bring detailed requirements into the factory to enable R&D for strong, robust, and successful product development.
• Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.
• Driving the deployment and smooth execution of SLM and Test solutions into customers' projects.
• Enabling customers to realize the value of silicon health monitoring using a robusta DFT framework throughout the lifecycle of silicon bring-up, validation, through in-field operations.

The Impact You Will Have:

• Enhancing Synopsys' Silicon Lifecycle Management (SLM) and DFT IP portfolio and end-to-end solution.
• Driving the adoption of Synopsys' SLM and DFT solutions at premier customer base worldwide.
• Influencing the development of next-generation SLM IPs and solutions.

What You'll Need:

• BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.

• 8 years of hands-on experience with DFT/BIST insertion, RTL design, and functional verification.

• Good exposure to JTAGIEEE 1149.1, IEEE 1687/1500, Testdata access mechanism.

• Knowledge on memory defectivities soft errors and reliability.

• Familiarity with error correcting codes such as Hamming and Hsiao.

• Hands-on experience in dealing with hierarchical SoCs, 1149.1/1500/1687 standards and pattern porting.

• Familiarity with either Synopsys TestMAX Tool chain or competitive offerings.

• Debugging abilities to identify and resolve issues in functional verification in UVM environment.

• Hands on experience in flow automation.

• Knowledge of Synthesis is a must with understanding of timing constraints (SDC).

• Knowledge of Lint, CDC, RDC is a plus.

• Knowledge of physical implementation is not a must, but good to have.

• Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions.

• Customer facing experience is a plus – educating/guiding customer on technical details of a solution.

• Good to have:

• Hands-on bring-up and debug experience of silicon is a plus.

• Architecture/micro-architecture experience.

• Understanding of GenAI and Agentic AI workflows.

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As an experienced and visionary ASIC digital design architect, you will thrive in a fast-paced, collaborative environment. You will bring a passion for solving complex system-level challenges and a track record of delivering innovative, high-quality silicon solutions.

Your deep understanding of IP and SoC architectures enables you to see the big picture while meticulously refining subsystem details. You are comfortable navigating ambiguity, building consensus across diverse teams, and translating product requirements into robust, scalable architectures.

Your leadership inspires those around you, and you excel at mentoring and empowering engineers to reach their full potential. You are adept at balancing trade-offs across performance, power, area, and security, always striving for the optimal solution.

Communication is your strength,you articulate technical concepts clearly to both technical and non-technical stakeholders, ensuring alignment and shared understanding.

With a growth mindset, you embrace new challenges, technologies, and methodologies, continuously seeking opportunities to innovate and improve.

You value inclusion and diversity, recognizing that the best ideas emerge from a culture where everyone feels empowered to contribute.

As an IP Subsystems Architect, you will define architectural specifications for complex subsystems, translate system-level requirements into detailed subsystem architectures, and integrate multiple IP blocks into cohesive subsystems.

You will lead cross-functional collaboration with hardware, software, verification, and physical design teams to ensure subsystem feasibility and correctness.

Establishing and guiding verification and validation strategies, including defining coverage requirements and participating in silicon bring-up and debug sessions.

Producing comprehensive architecture documents, specifications, and guidelines, and clearly communicating architectural intent to a wide range of stakeholders.

Mentoring and coaching engineers, driving best practices, and fostering a culture of technical excellence.

Shape the architecture of industry-leading silicon IP and subsystem solutions that power millions of devices worldwide.

Accelerate time-to-market for differentiated products by ensuring robust and efficient subsystem design and integration.

Reduce risk through rigorous requirements management, architectural clarity, and cross-functional alignment.

Enhance product performance, power efficiency, and reliability, directly impacting customer satisfaction and competitive advantage.

Foster innovation by mentoring teams, introducing new methodologies, and championing best practices.

Strengthen Synopsys’ position as a trusted technology leader in the semiconductor ecosystem.

Bachelor’s or Master’s degree in Electronics or a related field, with 15+ years of industry experience.

At least 10 years in semiconductor design, IP integration, or SoC/subsystem architecture roles.

Deep expertise in Verilog/SystemVerilog, simulation tools, and advanced verification methodologies (e.g., SV UVM, BFM development).

Proficiency with industry-standard interface protocols (AMBA APB/AXI/CHI, DDR, PCIe, Ethernet, USB, UFS, etc.).

Experience with synthesis, lint, CDC, low-power flows, and achieving verification closure.

Strong documentation and communication skills for effective cross-team alignment and requirements management.

A strategic thinker with exceptional leadership and mentoring capabilities.

A collaborative partner who thrives in diverse, cross-functional teams.

An excellent communicator, able to tailor messaging for both technical and non-technical audiences.

Innovative and proactive, always seeking opportunities to improve processes and outcomes.

Resilient and adaptable, comfortable with change and ambiguity.

Committed to fostering an inclusive and empowering team culture.

Join the Digital IP Subsystems Team at Synopsys,a high-performing group of architects, designers, and engineers focused on delivering world-class silicon IP and subsystem solutions.

The team collaborates closely with hardware, software, verification, and product teams across the globe, driving innovation in next-generation SoCs for AI, automotive, 5G, IoT, and more.

Together, we value creativity, technical excellence, and inclusion, empowering each team member to make a significant impact.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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As a Senior Manager of SOC Engineering, you will oversee and drive end-to-end RTL design, verification, architecture, and integration of advanced subsystems. You will lead teams in Bangalore/Hyderabad, manage customer communications, and ensure timely, high-quality delivery. You will guide your team through the full lifecycle: from requirements to release, ensuring excellence at every stage. Foster innovation and continuous improvement, motivating engineers to reach their full potential.

Key Qualifications:

• Bachelor's or Master's in Electronics or related field, with 15+ years of overall experience
• 8+ years of hands-on techno-managerial experience managing remote and local teams
• Strong track record in Subsystem/SoC design, architecture, and implementation
• Deep expertise in Verilog/System Verilog and simulation tools
• Proficiency with interface protocols (AMBA APB/AXI/CHI, DDR, PCIe, Ethernet, USB, UFS, etc.)
• Experience with synthesis, lint, CDC, low power flows, and verification closure (SV UVM, BFM development, test environment creation)
• Outstanding communication skills and a passion for team development

What Sets You Apart:

• You have strong, hands-on technical experience and thrive on rolling up your sleeves to solve complex challenges
• You excel at turning high-level requirements into innovative solutions and see projects through to successful, timely completion
• You build strong, trust-based relationships with customers and stakeholders, always putting their needs at the centre
• You bring a creative mindset and lead proactively, inspiring your team to think big, embrace change, and drive continuous improvement

Hands-on experience is an absolute must for success in this role.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted: 03/09/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.

You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.

With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.

Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.

What You’ll Be Doing:

• Lead and Drive all aspects of complete IP Design execution from start to end.

• Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.

• Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.

• Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.

• Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.

• Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.

• Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.

• Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.

The Impact You Will Have:

• Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.

• Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.

• Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.

• Enabling customers to achieve faster time-to-market and superior silicon performance.

• Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.

• Driving continuous improvement in design methodologies, enhancing efficiency and product quality.

• Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.

• 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.

• Past experience of leading IP deign projects, team.

• In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.

• Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.

• Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).

• Familiarity with scripting languages such as Perl or Shell—an advantage.

• Demonstrated ability to technically lead or mentor small teams of engineers.

Who You Are:

• A collaborative team player who thrives in a multi-site, multicultural environment.

• An effective communicator, able to translate complex technical concepts for diverse audiences.

• A proactive problem-solver with strong analytical and troubleshooting skills.

• Self-motivated, showing high initiative and ownership of responsibilities.

• Adaptable and eager to learn, always seeking opportunities for personal and professional growth.

• Committed to fostering a positive, inclusive, and innovative team culture.

The Team You’ll Be A Part Of:

You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.

As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.

The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world.

We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.

We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

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Responsibilities:

• Develop and deploy in-house tools and workflows to support engineering business units across NVIDIA.
• Take ownership of tools that verify common design blocks used in all products at NVIDIA.
• Act as a 'DevOps' engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.
• Build new workflows and methodologies to ensure smooth integration into various IP development environments.

Requirements:

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (or equivalent experience).
• 3+ years of proven experience preferred.
• Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.
• Proficiency in scripting using modern Python and/or Perl.
• Experience with Unix/Linux shell scripting and Makefiles.
• Strong ability to collaborate with multi-functional teams and effectively communicate technical details.

Preferred qualifications:

• Prior experience in ASIC verification.
• Knowledge of Clocks/Resets design and verification.
• Exposure to CDC related design/verification flows.
• Exposure to backend flows (Synthesis, Timing, etc).

NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of constant innovation and creating the highest performance products in the industry? If so, we want to hear from you.

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Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role you will:

• Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems

• Contribute to architectural studies including performance modeling and feasibility analysis.

• Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.

• Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.

• Build and review performance and functional models to validate design intent.

• Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.

You Might Thrive In This Role If You Have:

• Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.

• Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.

• Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.

• Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.

• Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.

• Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.

• Passion for building industry-leading massive-scale hardware systems.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

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RTL & Codesign Engineer

Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role you will:

• Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems

• Contribute to architectural studies including performance modeling and feasibility analysis.

• Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.

• Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.

• Build and review performance and functional models to validate design intent.

• Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.

You Might Thrive In This Role If You Have:

• Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.

• Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.

• Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.

• Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.

• Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.

• Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.

• Passion for building industry-leading massive-scale hardware systems.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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What you'll do

• Designing and verifying advanced digital circuits for PAM-based SerDes PHY IP, ensuring robust and high-performance mixed-signal solutions.
• Developing RTL code, modeling analog blocks, and crafting complex system-level testbenches in Verilog to validate functionality and performance.

What you need

• Bachelor's or Master's degree in Electrical Engineering (BSEE or MSEE) with at least 10 years of industry experience in digital design and verification.
• Must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is required
• Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows

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What you'll do

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

• Leading digital design and verification activities for advanced SERDES products, including Backplane Ethernet, PCIe, SATA, and USB 2/3.
• Analyzing and interpreting digital and analog specifications, ensuring seamless integration in mixed-signal environments.

What you need

• MSEE (preferred) or equivalent with a minimum of 5 years' experience in digital design and verification.
• Proven proficiency in Verilog or VHDL for ASIC development.
• Experience with code quality metrics and coverage-driven verification methodologies.
• In-depth knowledge of high-speed digital and mixed-signal design, asynchronous clock crossings, and DFT methodologies.
• Strong understanding of CDC, synthesis, and power optimization techniques.
• Hands-on experience with simulation tools and collaborative debugging in verification environments.
• Ability to develop system-level specifications for complex digital and analog systems.

What you'll be doing:

• Leading digital design and verification activities for advanced SERDES products, including Backplane Ethernet, PCIe, SATA, and USB 2/3.
• Analyzing and interpreting digital and analog specifications, ensuring seamless integration in mixed-signal environments.
• Driving the creation, execution, and tracking of comprehensive test plans, including functional, assertion, and code coverage metrics.
• Overseeing design flows for clock domain crossing (CDC), synthesis, design-for-test (DFT), and low-power methodologies.
• Collaborating closely with verification teams to debug issues, analyze failure cases, and run gate-level simulations.
• Coordinating with cross-functional teams and providing technical leadership throughout the product lifecycle, from specification development to performance testing of test chips.
• Mentoring and developing junior engineers, fostering a culture of continuous learning and innovation.

The Impact You Will Have:

• Accelerate the delivery of industry-leading mixed-signal ASIC solutions, enabling next-generation connectivity standards.
• Enhance the quality and reliability of high-speed SERDES products through rigorous design and verification practices.
• Drive process improvements that elevate team productivity and product performance.
• Champion best practices in digital and mixed-signal design, setting new benchmarks for quality and efficiency.
• Foster a collaborative and innovative team environment, empowering engineers to reach their full potential.
• Strengthen Synopsys' reputation as a global leader in semiconductor technology through successful project execution and customer satisfaction.

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