Job Description

As an experienced Analog Layout Senior Engineer, you will work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees. You will floor plan, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics. You will apply Analog Layout techniques to ensure design meets performance with minimum area and good yield. You will build and enhance layout flow for faster, higher quality design processes.

Responsibilities

• Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees.
• Floor plan, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics.
• Apply Analog Layout techniques to ensure design meets performance with minimum area and good yield.
• Build and enhance layout flow for faster, higher quality design processes.
• Perform layout verification for DRC/LVS/ERC/ANT/ESD/DFM.
• Conduct PERC verification for ESD/LUP checks.
• Complete all design quality checks and data quality checks.
• Collaborate with Place and Route engineers to integrate analog layouts into the top level.
• Work with the Package team to ensure the integration of top die and package.
• Participate in design reviews across the global team.
• Engage in package design, including interposer and RDL design.
• Collaborate closely with design teams in Vietnam, USA, Canada, and other countries to ensure the success of the whole product.
• Join research programs to implement new ideas for future products and flows.
• Lead a layout team to complete a full design block.
• Mentor junior layout engineers or interns.

Impact

• Drive the development of high-performance Analog IPs that power cutting-edge technologies.
• Enhance the layout design process for improved efficiency and quality.
• Ensure the robustness and reliability of our designs through meticulous verification processes.
• Contribute to the integration of complex layouts into top-level designs.
• Foster collaboration and knowledge sharing across global teams.
• Mentor and develop the next generation of layout engineers.

Requirements

• BS in Electronics Engineering, Electromechanics, Telecommunications.
• 2+ years of experience in custom layout.
• Proficiency with layout entry tools: Cadence, Synopsys.
• Experience with layout verification tools: Mentor Calibre, Synopsys ICV.
• Understanding of basic semiconductor fabrication processes and MOSFET fundamentals.
• Knowledge of high-speed layout techniques, ESD, Latchup, Antenna, EMIR.
• Experience mentoring/leading junior layout engineers.
• Ability to write layout review presentations and layout verification reports.
• Good English communication skills.

Team

You will join a dynamic and innovative team focused on developing high-performance Analog IPs. Our team collaborates closely with colleagues in Vietnam, USA, Canada, and other countries to ensure the success of our products. We value teamwork, knowledge sharing, and continuous improvement, and we are committed to fostering a supportive and inclusive work environment.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Sr Engineer, you will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. You will automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

Responsibilities:

• Develop and validate DRC, LVS, and Fill runsets for the Synopsys IC Validator tool
• Collaborate with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes
• Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python
• Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges
• Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions
• Mentor junior team members, share best practices, and contribute to a knowledge-sharing culture within the team

Impact:

• Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses
• Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market
• Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps
• Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges
• Contribute to the development of next-generation verification methodologies and best practices within Synopsys
• Strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support

Requirements:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field
• 5-8 years of hands-on experience in the Physical Verification (PV) domain
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks
• Exposure to competitive EDA tools and awareness of their strengths and limitations

Who You Are:

• An analytical thinker with strong problem-solving abilities and meticulous attention to detail
• A collaborative team player who fosters knowledge sharing and mentorship
• Effective communicator, capable of translating technical concepts to diverse audiences
• Adaptable and proactive, with a passion for continuous learning and innovation
• Customer-focused, with a commitment to delivering high-quality solutions on time
• Self-driven, organized, and able to manage multiple priorities in a fast-paced environment

The Team You’ll Be A Part Of:

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process

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You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience,primarily in Physical Verification (PV),you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

You are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements. As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment. Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions. You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies. Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python. Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions. Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team. Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

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You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Collaborating with local and international teams to develop layouts for complex analog and mixed-signal designs in advanced technology nodes (3nm, 2nm, and beyond).

Utilizing Synopsys suite of tools and full custom analog layout design tools (e.g., Custom Compiler) to create and optimize circuit layouts.

Implementing and verifying designs using industry-leading verification tools such as ICV, Calibre and Star-RCXT...

Developing SERDES sub-circuit layouts (RX, TX, PLL, etc.) and optimizing for signal integrity, including clock/data routes, differential routing, and shielding.

Applying scripting techniques (TCL, Python, etc.) to automate layout processes and improve workflow efficiency.

Ensuring designs meet ESD constraints, mitigate latch-up risks, and optimize for reliability issues such as EM and IR drop.

Designing custom digital logic cell layouts and associated logic path routing for mixed-signal integration.

Refining layouts to minimize parasitic effects and enhance matching, reliability, and performance.

Delivering high-quality IP that powers next-generation semiconductor products for global customers.

Enabling Synopsys to maintain leadership in advanced technology node design and IP development.

Contributing to the creation of reliable, high-performance silicon chips used in communications.

Driving innovation in analog and mixed-signal layout methodologies and tools.

Enhancing cross-team collaboration and knowledge sharing to accelerate project timelines and improve outcomes.

Ensuring robust design practices that minimize risk and maximize reliability, meeting stringent industry standards.

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As a Producer, you will: Produce on always-on, campaigns and Team Tilbury social content, including for Brand Ambassador Sofia Tilbury, from briefing to pre-production to shoot across moving image and stills Manage day-to-day execution of global content ensuring quality of outcomes for all weekly shoots and calendar planning Coordinate pre-production schedules, shoot schedules, optioning crew and creatives, call sheets, sourcing locations & hiring equipment Manage all shoot logistics Develop and maintain relationships with photographers, hair artists, set designers etc to ensure the highest possible level of talent Understand market rates and routinely negotiate the best rates possible with photographers, agents and agencies Contribute ideas to Creative leads on contributors to ensure content is on brand, and market leading Be resourceful and adaptable to changing budgets, timings and shifting priorities Prepare and communicate production schedules and timing plans in sync with the content and creative calendars Manage detailed record for usages contract, agreements and contracts for references Spearhead negotiations with agents to ensure the best possible deals for all shoot needs Responsible for bringing on board new talent and maintaining great relationships with external stakeholders such as photographers, directors, DOP, set designer & studios etc General daily admin – POs, budget tracking, Credit card expenses etc Management of freelance production assistants Manage relationships with external agencies and freelancers to ensure good working relationships are maintained Maintain a professional and productive working environment

Who you will work with Reporting to the Senior Producer

About you Thrives working within a fast-paced environment and be able to continually adapt Strong knowledge of and past experience in producing content for social channels Highly organised and pro-active with strong attention to detail to ensure the smooth running of all daily operations Depth of experience in shoot production with high calibre talent and artist portfolio Discreet and professional with excellent communications and networking skills Great relationship with top-tier photographers, talent/model/photographer agents Can prioritise tasks, use initiative and self-time management Be reliable, passionate and willing to think limitless Nimble and able to change direction easily and quickly Steady pair of hands who can deal with multiple stakeholders 2 years related experience within a production company or luxury brand

Why join us? Be a part of this values-driven, high-growth, magical journey with an ultimate vision to empower everyone, everywhere to be the best version of themselves We’re a hybrid model with flexibility, allowing you to work how best suits you 25 days holiday (plus bank holidays) with an additional day to celebrate your birthday Inclusive parental leave policy that supports all parents and carers throughout their parenting and caring journey Financial security and planning with our pension and life assurance for all Wellness and social benefits including Medicash, Employee Assist Programs and regular social connects with colleagues Bring your furry friend to work with you on our allocated dog-friendly days and spaces And not to forget our generous product discount and gifting!

At Charlotte Tilbury Beauty, our mission is to empower everybody in the world to be the most beautiful version of themselves. We celebrate and support this by encouraging and hiring people with diverse backgrounds, cultures, voices, beliefs, and perspectives into our growing global workforce. By doing so, we better serve our communities, customers, employees – and the candidates that take part in our recruitment process.

If you want to learn more about life at Charlotte Tilbury Beauty please follow our LinkedIn page!

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Defining and deploying advanced layout methodologies that accelerate execution, enhance quality, and promote standardized best practices across global teams.

Gathering customer requirements, translating them into clear technical specifications, and ensuring these specifications drive methodology and workflow development.

Developing end-to-end workflows that enhance quality, consistency, and efficiency across Synopsys IP development.

Collaborating closely with cross-functional teams—including Circuit Design, Physical Design, CAD, Product Engineering, and Quality—to enable adoption of methodologies for advanced technology nodes.

Providing technical leadership across distributed teams, aligning planning and execution to meet project goals.

Defining, tracking, and analyzing performance metrics to drive continuous improvement and influence future methodology strategy.

Creating and maintaining comprehensive documentation to ensure clarity, scalability, and long-term usability.

Engaging with internal partners and external customers as a trusted technical representative of the Methodology Team.

Leading innovation in analog/mixed-signal layout flows, combining industry-standard tools and internal automation to validate and evolve methodologies.

Mentoring and supporting junior engineers, enabling skill growth and knowledge sharing across the organization.

Accelerating and improving the reliability of analog/mixed-signal IP development at advanced nodes.

Driving alignment and quality across global design teams through standardized workflows and strong technical leadership.

Strengthening collaboration and knowledge transfer across engineering disciplines.

Influencing organizational and product strategy through methodology innovation and customer insights.

Increasing transparency and maintainability of workflows through high-quality documentation.

Contributing to reinforcing Synopsys’ position as a leader in semiconductor design technology.

5+ years in analog/mixed-signal layout or ASIC physical design, with experience in FinFET and advanced nodes strongly preferred.

Deep knowledge of analog and mixed-signal CMOS layout, device-level considerations, and chip-level integration.

Strong expertise with industry tools such as Synopsys Custom Compiler, Cadence Virtuoso, ICV, Calibre, and related verification flows.

Proven ability to gather customer requirements and convert them into technical specifications.

Demonstrated experience building workflows that improve IP quality, efficiency, and consistency.

Strong organizational skills, attention to detail, and ability to manage multiple complex initiatives simultaneously.

Excellent communication, leadership, and mentoring abilities.

Innovative and proactive in solving complex engineering challenges.

Collaborative, with a talent for working across interdisciplinary teams.

Strategic thinker who balances technical depth with big-picture vision.

Effective communicator, able to convey technical concepts to diverse audiences.

Mentor and coach, dedicated to supporting the growth of others.

Adaptable and resilient in fast-paced and evolving environments.

You will join the Mixed Signal IP Technology and Methodology Team—an advanced physical design group focused on developing full-custom analog and ASIC layout solutions for high-speed integrated circuits. The team is known for its collaborative culture, cutting-edge tool ecosystem, and strong commitment to innovation. As a Staff Engineer, you’ll work closely with experienced layout engineers, CAD specialists, and circuit designers to help define best-in-class methodologies and deliver high-quality solutions for Synopsys’ global customers.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are: You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

Responsibilities: Develop and validate DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies. Collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python. Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions. Mentor junior team members, share best practices, and contribute to a knowledge-sharing culture within the team. Stay up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

Impact: Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. Contribute to the development of next-generation verification methodologies and best practices within Synopsys. Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

Requirements: B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field. 5-8 years of hands-on experience in the Physical Verification (PV) domain. Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS. Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development. Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements. Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks. Exposure to competitive EDA tools and awareness of their strengths and limitations.

Who You Are: An analytical thinker with strong problem-solving abilities and meticulous attention to detail. A collaborative team player who fosters knowledge sharing and mentorship. Effective communicator, capable of translating technical concepts to diverse audiences. Adaptable and proactive, with a passion for continuous learning and innovation. Customer-focused, with a commitment to delivering high-quality solutions on time. Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

The Team You’ll Be A Part Of: You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

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What you'll do

• Designing and developing physical layouts for high-speed analog and mixed-signal IP blocks, including SerDes, RX, TX, PLL, and custom logic paths.
• Collaborating with a team of experienced layout engineers to deliver optimized, reliable, and manufacturable designs.

What you need

• BTech/MTech in Electronics or Electrical Engineering.
• 6+ years of hands-on experience in analog/mixed-signal IP layout and verification for high-speed analog circuits.

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