At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nAs a seasoned engineering professional with a passion for advancing electronic design automation (EDA) and CAD automation, you will thrive on solving complex technical challenges and enjoy collaborating with diverse teams to deliver robust, scalable solutions. Your expertise is rooted in front-end synthesis, timing constraints, and digital design flows, and you have a keen eye for detail and quality.
\nYou will design, develop, and enhance logic synthesis features and automation flows for industry-leading EDA solutions. You will own and maintain synthesis capabilities to optimize timing, area, power, and Quality of Results (QoR). You will develop and debug solutions across end-to-end EDA flows, understanding interactions between synthesis, place & route, STA, and power analysis tools.
\nYou will analyze and resolve complex customer and internal issues related to timing constraints (SDC), synthesis behavior, and flow integration. You will collaborate with architecture, verification, QA, and product management teams to deliver integrated, production-quality EDA solutions. You will participate actively in technical design discussions, code reviews, and roadmap planning to shape future product directions.
\nYou will ensure high engineering quality through unit testing, regression support, and adherence to best development practices. You will contribute to internal documentation, knowledge sharing, and mentoring junior engineers to foster team growth.
\nThe impact you will have includes enabling customers to achieve optimal timing, area, and power results in their ASIC and SoC designs. You will drive innovation in EDA automation, shaping the future of semiconductor design flows. You will improve product reliability, scalability, and integration across Synopsys' IP packaging and subsystem assembly solutions.
\nTo be successful in this role, you will need a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. You will require 6–8 years of experience in EDA tools, CAD automation, or system-level software development. You will need strong proficiency in C/C++ for large-scale software development.
\nYou will demonstrate a strong sense of ownership, accountability, and technical leadership. You will have clear and effective written and verbal communication skills to engage with technical and non-technical audiences. You will be able to work independently on complex problems while collaborating across teams.
\nYou will join a highly collaborative R&D team at Synopsys dedicated to advancing EDA tool development and automation. The team focuses on integrated design flows for IP packaging and subsystem assembly. You will work alongside talented engineers, architects, and product managers, contributing to innovative solutions that set industry standards and drive customer success.
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\nYou are a seasoned engineering leader with a passion for innovation and a deep understanding of physical design methodologies for cutting-edge semiconductor technologies. With a proven track record of successful project tape-outs, you thrive in collaborative, multidisciplinary environments, and you enjoy mentoring and guiding teams to achieve ambitious technical goals.
\nYour experience spans advanced FinFET nodes and the latest SERDES standards, and you possess a nuanced appreciation for both digital and mixed-signal architectures. You are methodology-driven, adept at software and scripting, and you have a strong grasp of CAD automation. Communication is your forte, whether you’re interfacing with peer groups, customers, or cross-functional teams.
\nLeading the physical implementation of advanced high-speed interface IPs and test-chips, from RTL to GDSII. Driving project execution for SERDES developments (56G/112G/224G PAM4/6) across multiple process nodes, including the latest FinFET technologies. Collaborating closely with front-end, analog, CAD, and product teams to ensure seamless integration and sign-off. Managing and mentoring a small team of engineers, fostering a culture of excellence, innovation, and continuous improvement. Developing and refining timing constraints and design architectures to ensure on-time delivery and optimal power/area targets. Applying advanced low-power design techniques and addressing the challenges of analog/digital interfaces in complex mixed-signal IPs. Contributing to methodology enhancements, CAD automation, and process improvement initiatives. Elevate Synopsys’ leadership in high-speed SERDES IP and mixed-signal solutions for next-generation silicon. Accelerate time-to-market for advanced interface IPs by ensuring robust and efficient physical implementation flows. Drive innovation in low-power and high-performance design, influencing industry standards and best practices. Mentor and empower engineering talent, building a high-performing team that delivers exceptional results. Strengthen cross-functional collaboration, optimizing integration and sign-off processes across technology domains. Enhance customer satisfaction through technical excellence, timely delivery, and superior product quality.
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\nThe impact you will have is accelerating time-to-market for Synopsys customers through robust, automated design flows. You will elevate the quality, reliability, and scalability of EDA methodologies and toolchains across multiple projects and technology nodes. You will influence the roadmap and strategic direction of Synopsys' automation and methodology offerings. You will empower engineering teams with state-of-the-art tools, training, and support to maximize productivity and innovation. You will enhance collaboration between R&D, application engineers, and customers by standardizing best practices and methodologies. You will reduce engineering overhead and manual intervention through data-driven process improvements and automation.
\nYou will need 10+ years of experience in EDA methodology, CAD automation, or semiconductor process development (analog, mixed-signal, or digital domains). You will have proven leadership, mentoring, and project management skills in a cross-functional engineering environment. You will have deep hands-on expertise with industry-standard EDA tools (e.g., Synopsys Custom Compiler, Cadence Virtuoso, Calibre, ICV, or similar). You will have strong programming and scripting skills in Python, Perl, TCL, Shell, SKILL, or related languages, with a focus on automation and tool integration.
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\nWhat you'll do
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\nAs a R&D Engineering Manager, you will lead the planning, execution, and delivery of R&D initiatives focused on methodology and automation improvements.
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