We Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nYou Are:
\nYou are a hands-on technical leader with extensive experience in mixed-signal verification and ASIC development. You excel at implementing sophisticated test plans and sharing best practices with project owners to ensure seamless execution. Your expertise in high-speed protocols, verification environments, and automation scripting positions you to drive successful product delivery and technical excellence. You are passionate about leveraging your skills to mentor others, optimize workflows, and contribute to a culture of innovation and collaboration. Your approach is both solution-oriented and inclusive, ensuring every team member has the opportunity to contribute and grow.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou’ll join a multidisciplinary engineering team advancing silicon IP solutions for global customers. The team is comprised of industry experts focused on mentorship, technical excellence, and continuous improvement in a respectful, inclusive environment.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_7a3a24a8-685","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/mississauga/asic-digital-design-principal-engineer-13370/44408/88584170960","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC development","Mixed-signal verification","High-speed protocols","Verification environments","Automation scripting","SystemVerilog","UVM methodology","PCIe","Ethernet protocols","Digital signal processing"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:17:02.939Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mississauga"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC development, Mixed-signal verification, High-speed protocols, Verification environments, Automation scripting, SystemVerilog, UVM methodology, PCIe, Ethernet protocols, Digital signal processing"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4f7dae70-9ee"},"title":"R&D Engineer, Staff (PD, PnR, CTS)","description":"Join Synopsys as a Staff R&D Engineer in Physical Design (PD), Place and Route (PnR), and Chip Technology Software (CTS). As a member of our Hardware-Analytics and Test (HAT) business unit, you will be part of the SLM Hardware Group (SHG) developing advanced SLM IPs and subsystems.
\nKey Responsibilities:
\nImpact:
\nRequirements:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou’ll join the rapidly expanding Hardware-Analytics and Test (HAT) business unit as a member of the SLM Hardware Group (SHG). The team is dedicated to developing advanced SLM IPs and subsystems, leveraging expertise in backend and physical design to deliver robust, high-performance solutions.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_4f7dae70-9ee","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/r-and-d-engineer-staff-pd-pnr-cts/44408/93647959680","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDS physical implementation","Synthesis","Static timing analysis","Place and route","Layout closure","Automation scripting","TCL/PERL","EDA tools","Synopsys PrimeTime","ICC2","Design Compiler","Fusion Compiler","Soft and mixed-signal IPs","High-frequency/multi-voltage designs","Low-power methodologies","PVT-sensors","DFT/DFx technologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:12:09.026Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDS physical implementation, Synthesis, Static timing analysis, Place and route, Layout closure, Automation scripting, TCL/PERL, EDA tools, Synopsys PrimeTime, ICC2, Design Compiler, Fusion Compiler, Soft and mixed-signal IPs, High-frequency/multi-voltage designs, Low-power methodologies, PVT-sensors, DFT/DFx technologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6c3773cd-28f"},"title":"Lead RTL Verification Engineer","description":"Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nYou are an accomplished engineer with a passion for digital design and verification, eager to make a lasting impact in advanced semiconductor technology. With over a decade of hands-on experience, you bring technical mastery and strategic vision to every project. You thrive in dynamic environments, seamlessly balancing architectural planning with hands-on execution. Your expertise spans RTL development, mixed-signal IPs, and advanced verification methodologies, making you a go-to authority for complex challenges.
\nAs a Lead RTL Verification Engineer, you will be responsible for architecting and implementing SystemVerilog/UVM-based testbenches and verification flows for mixed signal IPs such as UCIe/DDR/Die-to-Die interfaces. You will develop, execute, and drive closure for comprehensive verification plans and coverage metrics. You will also debug RTL issues, manage regressions, and lead root cause analysis for failures.
\nGuiding and mentoring junior engineers, establishing verification standards and best practices, collaborating with design, software, and validation teams to ensure seamless project delivery and integration, evaluating and championing new verification tools, automation scripts, and methodologies to drive innovation.
\nElevate the quality and reliability of Synopsys' mixed signal IPs, directly impacting the success of global semiconductor partners. Accelerate innovation in chip design and verification, contributing to industry-leading products and solutions. Mentor and empower the next generation of engineers, fostering a culture of excellence and growth. Drive adoption of best-in-class verification standards, enhancing productivity and efficiency across teams. Enable seamless integration of complex IPs by bridging design, software, and validation disciplines. Champion advanced verification technologies, positioning Synopsys as a leader in digital design automation.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_6c3773cd-28f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/lead-rtl-verification-engineer/44408/93635748416","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design and verification","SystemVerilog/UVM","mixed-signal IPs","advanced verification methodologies","EDA tools","regression management","automation scripting","standard protocol verification","CAD environments"],"x-skills-preferred":["AI/ML technologies","gate-level netlist creation","advanced verification techniques"],"datePosted":"2026-04-24T14:11:29.188Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, SystemVerilog/UVM, mixed-signal IPs, advanced verification methodologies, EDA tools, regression management, automation scripting, standard protocol verification, CAD environments, AI/ML technologies, gate-level netlist creation, advanced verification techniques"}]}