Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.
\nThe role involves intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nAs a DFT Junior Engineer, you will own DFT tasks, create timing constraints for mission and DFT modes, work with design and implementation teams, support customer IP integration and silicon bring-up, automate workflows with scripting, and mentor junior team members.
\nThe impact you will have includes enhancing IP core testability and quality, accelerating time-to-market for new chipsets, facilitating seamless SoC integration, promoting best practices and team growth, advancing DFT methodologies at Synopsys, and supporting customers during silicon bring-up.
\nTo be successful in this role, you will need a degree in Electronics, Electrical Engineering, or a related field, no DFT experience required for junior roles, knowledge of scan insertion, ATPG, JTAG, experience with Synopsys tools (Design Compiler, VCS, TetraMAX) preferred, and scripting skills (Perl, TCL, Python).
\nYou will be an analytical, detail-oriented, proactive, collaborative and communicative individual who is adaptable and eager to learn.
\nJoin a skilled DFT engineering team that values collaboration, innovation, and technical excellence. Benefit from mentorship and tackle industry-leading challenges together.
\nWe offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more about salary and benefits during the process.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_c12edbfc-7a0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/dft-junior-engineer-in-hcmc-ha-noi-da-nang/44408/92864858752","x-work-arrangement":"onsite","x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["scan insertion","ATPG","JTAG","Synopsys tools (Design Compiler, VCS, TetraMAX)","scripting skills (Perl, TCL, Python)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:23:13.711Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"scan insertion, ATPG, JTAG, Synopsys tools (Design Compiler, VCS, TetraMAX), scripting skills (Perl, TCL, Python)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_be7395ea-310"},"title":"Product Manager Memory Test","description":"Engineer the Future with Us
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\nProduct Manager Memory Test
\nSunnyvale, California, United States
\nSave
\nCategory: Product ManagementHire Type: Employee
\nJob ID 16239Base Salary Range $183000-$274000Date posted 03/17/2026
\nYou are an experienced leader with a strong understanding of the entire IC design flow from architectural definition through physical implementation and signoff with a focus on design-for-test (DFT), automatic test pattern generation (ATPG), built-in-self-test (BIST) and yield diagnostics. You are intimately familiar with in-system and manufacturing test market, design techniques and methodologies, customer requirements, and industry landscape. You exhibit solid cross-functional skills to work with senior customer engineering management, Synopsys’ leadership, and collaborate with strong R&D and Product Engineering teams. You thrive in the EDA or semiconductor sector as a senior product manager or marketer – ideally in the San Francisco Bay Area.
\nWhat You’ll Be Doing:
\nTracking engagement pipeline and key milestones to meet goals through cross-functional collaboration and driving business and technical objectives.
\nServing as a subject matter expert internally and externally, interacting with customers and field teams.
\nMonitoring market and competitive trends, feeding insights back into product and leadership teams to adjust strategies and execution as needed.
\nThe Impact You Will Have:
\nDirecting the product road map development in collaboration with cross-functional teams.
\nCreating impactful marketing and customer campaigns, outbound initiatives, and compelling collateral to elevate product visibility.
\nProviding market and competitive insights to perform strategic adjustments and maintain a competitive edge.
\nWhat You’ll Need:
\n10+ years of relevant design/EDA experience, specifically in product management or marketing.
\nBS or MS degree in Electrical Engineering, or similar; MBA/PHD is plus.
\nStrong collaborative and cross-functional skills to work in a matrix environment with solid organizational skills and a flexible mindset.
\nExcellent presentation, oral/written communication skills in English, and interpersonal skills.
\nCustomer-centric approach and ability to engage effectively with diverse stakeholders both within and outside the company.
\nThe Team You’ll Be a Part Of:
\nYou will be part of a highly skilled and collaborative team focused on driving Synopsys’ leadership in DFT, BIST & ATPG area. In addition to you as the product management leader, this team is composed of experts in R&D, Product Engineering, and Field Applications Engineering, all working together to drive success via customer adoption of Synopsys manufacturing test products.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_be7395ea-310","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/product-manager-memory-test/44408/92936862624","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"Employee","x-salary-range":"$183000-$274000","x-skills-required":["Design-for-Test (DFT)","Automatic Test Pattern Generation (ATPG)","Memory Test & Repair","In-system and manufacturing test market","Design techniques and methodologies","Customer requirements","Industry landscape"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:35.757Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"occupationalCategory":"Product Management","industry":"Technology","skills":"Design-for-Test (DFT), Automatic Test Pattern Generation (ATPG), Memory Test & Repair, In-system and manufacturing test market, Design techniques and methodologies, Customer requirements, Industry landscape","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":183000,"maxValue":274000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c9605b6a-5ba"},"title":"DFT Senior/Staff Engineer","description":"Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nAs a DFT Senior/Staff Engineer, you will own DFT tasks at IP level, including scan chain stitching, ATPG, and simulation. You will create timing constraints for mission and DFT modes, work with design and physical implementation teams on synthesis and constraint validation, support customer IP integration and silicon bring-up, and lead and coach DFT team members.
\nThe impact you will have includes improving testability and quality of IP cores, speeding up time-to-market for new chips, supporting seamless SoC integrations for customers, and mentoring team members and sharing best practices.
\nTo be successful in this role, you will need a BS/MS/PhD in Electronics or a related field, 2+ years DFT design experience, expertise in scan insertion, ATPG, JTAG, and experience with Synopsys tools (Design Compiler, VCS, TetraMAX) is a plus. You will also need scripting skills (Perl, TCL, Python) and be detail-oriented, analytical, and a strong communicator.
\nJoin our expert DFT Engineering team in Ho Chi Minh City, dedicated to advancing testability and reliability in semiconductor IP.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_c9605b6a-5ba","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/dft-senior-staff-engineer-in-hcmc-ha-noi-da-nang/44408/90071446368","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["scan insertion","ATPG","JTAG","Synopsys tools","scripting skills"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:48.960Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"scan insertion, ATPG, JTAG, Synopsys tools, scripting skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4b712e08-c1e"},"title":"Staff Engineer (Machine Learning)","description":"Job Description
\nAt Synopsys, we're seeking a Staff Engineer (Machine Learning) to join our Machine Learning Center of Excellence (ML CoE) within our Silicon Design & Verification business. As a key member of this highly innovative team, you'll be responsible for designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.
\nKey Responsibilities:
\nImpact:
\nRequirements:
\nWho We're Looking For:
\nThe Team You'll Be A Part Of:
\nYou'll join the Machine Learning Center of Excellence (ML CoE) within Synopsys' Silicon Design & Verification business. This highly innovative team is at the forefront of integrating AI and ML into chip design, collaborating with experts across architecture, implementation, and verification. Together, you'll drive the development of ML-based design optimization solutions and set new standards for the semiconductor industry.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_4b712e08-c1e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/dublin/staff-engineer-machine-learning/44408/92577691360","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["machine learning","chip design","EDA","Perl","Python","Tcl","shell scripting","Unix/Linux environments","design flow automation","RTL design","synthesis","place and route","verification","ATPG","custom-circuit design","signoff flows","low power design techniques","computer architecture"],"x-skills-preferred":[],"datePosted":"2026-03-10T12:09:01.596Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Dublin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"machine learning, chip design, EDA, Perl, Python, Tcl, shell scripting, Unix/Linux environments, design flow automation, RTL design, synthesis, place and route, verification, ATPG, custom-circuit design, signoff flows, low power design techniques, computer architecture"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_46cf12da-6c5"},"title":"ASIC Digital Design, Principal","description":"We Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nYou Are:
\nYou are a skilled and passionate engineer with deep expertise in system design, embedded firmware, digital design, and verification with over 15 years of impactful experience. You are a highly accomplished engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry.
\nA technical powerhouse as well as subject matter expert in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results.
\nYou bring a deep understanding of system, digital, firmware design, high-speed memory interface architectures. Your experience includes leading multi-disciplinary teams, driving technical roadmaps, and mentoring engineers to deliver best-in-class solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.
\nWhat You'll Be Doing:
\nThe Impact You Will Have:
\nWhat You'll Need:
\n15+ years of experience in Firmware, ASIC design, verification, system validation, and technical leadership roles.
\nBe results driven
\nProven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.
\nAdvanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.
\nIn-depth knowledge of system-level validation for high-speed interface PHY
\nProven track record of working cross-functionally and driving issues to closure
\nKnowledge of mixed-signal design
\nExperience in working in cross-functional collaborations
\nBe an excellent communicator and a beacon for change
\nExcellent debugging, analytical, and problem-solving skills
\nWorking knowledge of scripting in languages such as Python and/or Perl
\nGood understanding of DFT, ATPG, and design for debug techniques and their application in testing of silicon
\nGood interpersonal skills, ability & desire to work as a standout colleague
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nInclusion and Diversity:
\nInclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
\n#LI-DP1
\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
\nBenefits:
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_46cf12da-6c5","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/asic-digital-design-principal-15193/44408/91882458064","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Firmware","ASIC design","verification","system validation","technical leadership","UVM methodology","System Verilog","MATLAB","Perl","Python","C++","high-speed memory interface architectures","mixed-signal design"],"x-skills-preferred":["Shell","Perl","Python","C++","DFT","ATPG","design for debug techniques"],"datePosted":"2026-03-09T11:03:54.840Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean, Ontario, Canada"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Firmware, ASIC design, verification, system validation, technical leadership, UVM methodology, System Verilog, MATLAB, Perl, Python, C++, high-speed memory interface architectures, mixed-signal design, Shell, Perl, Python, C++, DFT, ATPG, design for debug techniques"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b4e4a0dc-158"},"title":"DFT, Staff Engineer","description":"Overview
\nAt Synopsys, our Hardware Engineers are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nJob Description
\nCategory
\nEngineering
\nHire Type
\nEmployee
\nJob ID
\n15995
\nRemote Eligible
\nNo
\nDate Posted
\n03/05/2026
\nAlternate Job Titles:
\nWe Are:
\nAt Synopsys, we drive innovations that shape the way we live and connect. From smart cars to AI, our technology leads chip design and verification worldwide. Join us to transform the future through continuous innovation.
\nYou Are:
\nYou are a proactive engineer with 5+ years of DFT experience, strong communication skills, and a drive for technical excellence. You enjoy teamwork, learning, and solving complex challenges in digital design.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nJoin a skilled, diverse engineering team in Da Nang focused on advancing DFT methodologies and supporting global innovation.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will provide more details during the hiring process.
\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
\n\\\\ Benefits vary by country and region - check with your recruiter to confirm
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_b4e4a0dc-158","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hanoi/dft-staff-engineer-in-hcmc-hanoi/44408/92454718736","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["DFT design experience","Scan insertion","ATPG","JTAG","Synopsys tools (Design Compiler, VCS, TetraMAX)","Scripting (Perl, TCL, Python)"],"x-skills-preferred":[],"datePosted":"2026-03-08T22:19:13.522Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hanoi"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"DFT design experience, Scan insertion, ATPG, JTAG, Synopsys tools (Design Compiler, VCS, TetraMAX), Scripting (Perl, TCL, Python)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4d07cae6-e76"},"title":"Solutions Staff DFT Engineer","description":"We are seeking a Solutions Staff DFT Engineer to join our team. As a Solutions Staff DFT Engineer, you will be responsible for delivering comprehensive DFT solutions to customers designing digital ICs of varying complexity, from integration through silicon bring-up. You will provide technical expertise during design planning, budgeting, and implementation phases for test solutions. You will also implement and validate DFT Solutions for Scan/MBIST/1687, including architecture planning, pattern generation, silicon bring-up, and diagnostics analysis.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_4d07cae6-e76","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/solutions-staff-dft-engineer/44408/91204625424","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL coding","DFT insertion","ATPG","IEEE standards","MBIST concepts","silicon bring-up"],"x-skills-preferred":["scan architectures","fault models","pattern generation","simulation","test access networks","scan flows"],"datePosted":"2026-03-06T07:23:43.327Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL coding, DFT insertion, ATPG, IEEE standards, MBIST concepts, silicon bring-up, scan architectures, fault models, pattern generation, simulation, test access networks, scan flows"}]}