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  <jobs>
    <job>
      <externalid>b5f1283c-76e</externalid>
      <Title>ASIC Digital Design, Sr Staff/Principal Engineer - DDR</Title>
      <Description><![CDATA[<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>
<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>
<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>
<p><strong>Job Description</strong></p>
<p><strong>Date posted</strong>: 03/09/2026</p>
<p><strong>We Are:</strong></p>
<p>At Synopsys, we drive the innovations that shape the way we live and connect.</p>
<p>Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>
<p>We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>
<p>Join us to transform the future through continuous technological innovation.</p>
<p><strong>You Are:</strong></p>
<p>You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.</p>
<p>You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.</p>
<p>With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.</p>
<p>Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.</p>
<p><strong>What You’ll Be Doing:</strong></p>
<ul>
<li>Lead and Drive all aspects of complete IP Design execution from start to end.</li>
</ul>
<ul>
<li>Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.</li>
</ul>
<ul>
<li>Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.</li>
</ul>
<ul>
<li>Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.</li>
</ul>
<ul>
<li>Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.</li>
</ul>
<ul>
<li>Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.</li>
</ul>
<ul>
<li>Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.</li>
</ul>
<ul>
<li>Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.</li>
</ul>
<p><strong>The Impact You Will Have:</strong></p>
<ul>
<li>Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.</li>
</ul>
<ul>
<li>Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.</li>
</ul>
<ul>
<li>Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.</li>
</ul>
<ul>
<li>Enabling customers to achieve faster time-to-market and superior silicon performance.</li>
</ul>
<ul>
<li>Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.</li>
</ul>
<ul>
<li>Driving continuous improvement in design methodologies, enhancing efficiency and product quality.</li>
</ul>
<ul>
<li>Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.</li>
</ul>
<p><strong>What You’ll Need:</strong></p>
<ul>
<li>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.</li>
</ul>
<ul>
<li>10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.</li>
</ul>
<ul>
<li>Past experience of leading IP deign projects, team.</li>
</ul>
<ul>
<li>In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.</li>
</ul>
<ul>
<li>Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.</li>
</ul>
<ul>
<li>Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).</li>
</ul>
<ul>
<li>Familiarity with scripting languages such as Perl or Shell—an advantage.</li>
</ul>
<ul>
<li>Demonstrated ability to technically lead or mentor small teams of engineers.</li>
</ul>
<p><strong>Who You Are:</strong></p>
<ul>
<li>A collaborative team player who thrives in a multi-site, multicultural environment.</li>
</ul>
<ul>
<li>An effective communicator, able to translate complex technical concepts for diverse audiences.</li>
</ul>
<ul>
<li>A proactive problem-solver with strong analytical and troubleshooting skills.</li>
</ul>
<ul>
<li>Self-motivated, showing high initiative and ownership of responsibilities.</li>
</ul>
<ul>
<li>Adaptable and eager to learn, always seeking opportunities for personal and professional growth.</li>
</ul>
<ul>
<li>Committed to fostering a positive, inclusive, and innovative team culture.</li>
</ul>
<p><strong>The Team You’ll Be A Part Of:</strong></p>
<p>You will join the R&amp;D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.</p>
<p>As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.</p>
<p>The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.</p>
<p><strong>Rewards and Benefits:</strong></p>
<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>
<p>Our total rewards include both monetary and non-monetary offerings.</p>
<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>
<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.</p>
<p>Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>
<p><strong>Benefits</strong></p>
<p>At Synopsys, innovation is driven by our incredible team around the world.</p>
<p>We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.</p>
<p>We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>
<p>Visit Benefits Page</p>
<ul>
<li>### Health &amp; Wellness</li>
</ul>
<p>Comprehensive medical and healthcare plans that work for you and your family.</p>
<ul>
<li>### Time Away</li>
</ul>
<p>In addition to company holidays, we have ETO and FTO Programs.</p>
<ul>
<li>### Family Support</li>
</ul>
<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>
<ul>
<li>### ESPP</li>
</ul>
<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>
<p style="margin-top:24px;font-size:13px;color:#666;">XML job scraping automation by <a href="https://yubhub.co">YubHub</a></p>]]></Description>
      <Jobtype>full-time</Jobtype>
      <Experiencelevel>senior</Experiencelevel>
      <Workarrangement>onsite</Workarrangement>
      <Salaryrange></Salaryrange>
      <Skills>RTL design, System architecture, ASIC solutions, High-performance protocols, DDR PHY, PCIe, USB, HBM, Verilog, SystemVerilog, Simulation tools, Design flows, Lint, CDC, Synthesis, Static timing analysis, Formal verification, Control path-oriented designs, Asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces, Scripting languages, Perl, Shell</Skills>
      <Category>Engineering</Category>
      <Industry>Technology</Industry>
      <Employername>Synopsys</Employername>
      <Employerlogo>https://logos.yubhub.co/careers.synopsys.com.png</Employerlogo>
      <Employerdescription>Synopsys is a leading provider of electronic design automation (EDA) software and intellectual property (IP) used in the design and manufacturing of semiconductors.</Employerdescription>
      <Employerwebsite>https://careers.synopsys.com</Employerwebsite>
      <Compensationcurrency></Compensationcurrency>
      <Compensationmin></Compensationmin>
      <Compensationmax></Compensationmax>
      <Applyto>https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-principal-engineer-ddr/44408/92599737760</Applyto>
      <Location>Bengaluru, Karnataka, India</Location>
      <Country></Country>
      <Postedate>2026-03-10</Postedate>
    </job>
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